The SmartSpice Interface to Cadence (revisited)

The SmartSpice interface to the Cadence Design Framework II has been substantially improved in its latest release (version 1.0.8.R), following feedback from a number of existing users. The interface is implemented through the Cadence Spice Socket, and enables users of Cadence's Analog Artist and Composer software to interact directly, and seamlessly, with SmartSpice. The interface works through a series of Analog Artist control screens implemented by Silvaco using the Cadence OASIS interface. Because it depends on the sophisticated functionality provided by OASIS, the SmartSpice/Spice Socket interface is only compatible with version 4.4.0 (and above) of the Design Framework. SmartSpice is also compatible with the HSPICE Socket built into older versions of Cadence's Composer, Edge and Artist products, although access through this interface to SmartSpice's more powerful features is necessarily limited. The improvements described in this article take the form of a series of enhancements (including some bug fixes) which have been made to several of the existing interface features. These improvements are part of an on-going project aimed at making the SmartSpice interface provide access to substantially more of the features available in SmartSpice itself than was the case in earlier releases.

One important feature, fixed in this release, is the generation of hierarchical netlists from Analog Artist, and the ability to correctly annotate sub-circuit simulation information back to the Composer schematic window. The ability to annotate operating points and currents has also been fully implemented for all component types. An example of a fully annotated subcircuit is illustrated in Figure 1. The functionality of the analysis control screens in Analog Artist will be greatly enhanced in the next release of the SmartSpice interface; the first step in this direction has already been taken in the current release, however, in the form of a set of control items providing the ability to save bias points in both DC and transient analyses.

 

Figure 1. An example of subcircuit back annotation.

 

 

Several components of the Cadence design library 'analogLib' did not allow the instantiation of SmartSpice views on the Cadence Composer schematic editor in previous releases of the SmartSpice interface; an example is the file-based, piece-wise linear voltage source (vpwlf). This behavior has been corrected in the current release. Furthermore, none of the voltage sources in the analogLib library were annotating their operating currents to the schematic editor in the last release. This problem has been rectified in version 1.0.8.R, and the characteristics of both voltage and current sources have been extended so that, where appropriate, the power is also annotated to the schematic.

In summary, then, a brief, but complete list of features implemented in the current release of the SmartSpice interface to the Cadence Design Framework II is:

  • Ability to specify SmartSpice as the default simulator in the Setup->Simulator/Directory/Host control screen of Analog Artist.
     
  • Ability to include model files in SmartSpice or cdsSpice format in the Setup->Environment control screen of Analog Artist.
     
  • Ability to generate PSF output from SmartSpice, implemented through automatic generation of the "psf=2" option.
     
  • Annotation of node voltages to the Composer schematic editor, selected via the Results->Annotate-> DC Node Voltages menu item in Analog Artist.
     
  • Annotation of device operating points (for example, device currents, gds, etc.) to the Composer schematic editor, selected via the Results->Annotate->DC Operating Points menu item in Analog Artist, and controlled via the opPointLabelSet field of the Interpreted Labels Information section of the CDF properties in the Silvaco-supplied analogLib library, accessed via the Tools->CDF->Edit control screen in the Cadence CIW.
     
  • Support for marching waveforms, implemented via the SmartSpice waveform viewer through automatic generation of the ".IPLOT" statement.
     
  • Direct plot of waveforms in the Cadence Waveform Window, implemented via the Results->Direct Plot menu in Analog Artist, combined with user selection in the Composer schematic editor.
     
  • Hierarchical netlisting capability, implemented through SmartSpice/Spice Socket name mapping routines in the OASIS interface.
     
  • New Silvaco-supplied versions of the Cadence basic and analogLib libraries, incorporating SmartSpice views of all appropriate devices.
     
  • Compatibility with ac, dc, transient and noise analyses, via the Choosing Analyses control screen in Analog Artist.
     
  • Ability to save bias points in dc and transient analyses, via the Choosing Analysis control screen in Analog Artist.
     
  • Ability to configure the following SmartSpice options from within the Simulator Options control screen in Analog Artist:
ABSTOL, ACCT, ACCURATE, ACM, AUTOSTOP, BYPASS, CAPDC, CAPMOD, 
CAPTAB, CHGTOL, COEF1, CONV, DCGMCHK, DCGMIN, DCGMSTEPS, DCIAP, 
DCPATH, DEFAD, DEFAS, DEFL, DEFPD, DEFPS, DEFNRD, DEFNRS, DEFW, 
DISTRIBUTION, EXPERT, FORMAT, GMIN, GMINSTEPS, HDIF, ICG, 
INTEGR, INTERP, ITL1, ITL2, ITL4, ITL41, ITL5, LD, LDIF, LIMPTS, 
LIST, LOGIC, METHOD, NODE, NOMOD, NOPAGE, NUMDGT, OPTS, PIVREL, 
PIVTOL, RAWPTS, RELTOL, SCALE, SCALM, SRCSTEPS, TEMP, TNOM, TRTOL, 
TRYTOCOMPACT, TTICK, VNTOL, VSTA, VZERO, WIDTH

The main aspect of the next release will be a complete rewrite of the SmartSpice analysis control screens in Analog Artist, adding support for more specialized SmartSpice functionality, including:

  • Support for the "CallV"/"SaveV" and "UIC" options in AC and DC analyses.
     
  • Support for the "TRANOP" calculation of operating point option.
     
  • Support for the specification of a maximum internal step in transient analysis.
     
  • Support for the specification of the options "RAWPTS", "INTERP", etc. in transient analysis.
     
  • Support for nested sweeps of device, parameter, or temperature in AC and DC analyses.
     
  • Support for the specification of maximum iterations, tolerances, etc. in DC analysis.