Introduction

By designing specifically for MESFETs and HEMTs Silvaco has optimized device simulation algorithms to produce a new and highly efficient simulation framework to be released as FastATLAS. Simulations with FastATLAS are typically 1000 to 10000 times faster than ATLAS allowing truly interactive TCAD. FastATLAS includes all the relevant physical models currently available within the ATLAS framework, maintaining simulation accuracy while delivering unprecedented speed.

FastATLAS and ATLAS were both used to simulate a 0.5 micron gate length recessed GaAs MESFET structure. The ATLAS structure contained 2700 nodes and averaged around 55 seconds per bias point on a SUN Sparc ULTRA workstation. The same structure was simulated with FastATLAS which automatically generated a mesh using over 15000 nodes yet reduced the simulation time to 7.5 milliseconds per bias point, a speed increase by a factor of 7000! FastATLAS timings for typical analyses are given in Figure 1.

 

FastAtLAS Simulation Timings

Type of Analysis CPU Time on
Sun SPARC 20
Charge Control analysis 24 seconds
DC Id/Vds family 2.6 seconds
(drift-diffusion, 119 points)
DC Id/Vds family 1.4 seconds
(energy balance, 99 points)
DC Id/Vgs sweep 2.5 seconds
(energy balance, 21 points)
Rf rapid 1.3 seconds
(energy balance, 33 points)
Rf full-period 2.5 seconds
(energy balance, 128 points)
Rf swept - full period 59 seconds
(energy balance, 7552 points)
Figure 1. All simulations were on a 0.5µm gate length recessed MESFET. The DC-IV simulations were taken over the range -2<Vgs<0, 0.5 volt increments, 0<Vds<5, 0.1 volt increments. The Id/Vgs sweep was taken over the range -2<Vgs<0, 0.1 volt increment Vds = 0.1 volts. The RF simulations were taken at the bias point Vgs = 0, Vds = 2 volts, freq = 20 GHz, and the RF swept simulation was taken at Vgs = 0, Vds = 2 volts 1<freq<30 GHz, 0.5 Ghz increment.

 

 

Figure 2. Small-signal RF simulaton of a GaAs/AlGaAs/ GaAs HEMT
biased at 0 volts VGS, 2 volts VDS. Frequency sweeps from
1 Ghz to 25 GHz in 1GHz intervals.

FastATLAS Architecture

The complete suite of FastATLAS modules is illustrated in Figure 3. The core simulator incorporates the physical models present in ATLAS including complex effects such as energy-balance and velocity overshoot. These features are coupled with a comprehensive material parameter database, input parser, c-interpreter and several post-processing options including various two-port and equivalent circuit extraction algorithms. FastATLAS has been designed to be user friendly and includes several features to enable ease of use. One important development has been the inclusion of an automatic mesh generation algorithm, relieving the user from this arduous and time-consuming task. The speed of the simulation process enables FastATLAS to perform trial solutions using an exceptionally dense mesh, typically with only two Angstrom node spacing. The solutions are then analyzed and a non-uniform mesh generated that maintains solution accuracy and enables high simulation speed. A typical mesh generated by FastATLAS is shown in Figure 4, illustrating the clustering of nodes, especially at the drain edge of the gate. In addition the solution sequence has been automated. In FastATLAS it is not necessary to specify solution techniques since the simulation procedure automatically and robustly solves for all biases. Combining these features produce a flexible simulation tool able to rapidly characterize arbitrary FET structures.

 

Figure 3. Architecture of FastATLAS framework.

 

 

Figure 4. Mesh layout around the gate, automatically generated within FastATLAS. Typical mesh size at drain edge of gate 2.8 x 0.6nm.

 

Module Description

FASTBlaze, is the simulator that solves DC single point and swept IV simulation and the small-signal time-domain RF single point and swept bias simulations. One of the benefits of an extremely fast simulation is that one can perform time-domain simulations. This is done within FastATLAS and forms the basis of the RF simulator. In the small-signal simulation sinusoid input signals are applied to the terminals and their effects monitored. The user can then select from time-domain or a variety of two-port output options.

FastGiga incorporates the lattice heat flow equations into FastBlaze accounting for thermal effects, particularly important in power applications. One new development is to include a comprehensive transport parameter database derived from an ensemble Monte Carlo simulation. The transport models implicitly include the effects of field, doping and importantly for FastGiga, lattice temperature.

FastNOISE is capable of extracting noise parameters for a simulated device. This simulation incorporates a variety of noise mechanisms and uses the impedance-field method to obtain the terminal characteristics. Again several post-processing options are available allowing FastNOISE to output the conventional noise parameters: Fmin, Rn and Gopt.

FastMixedMode embeds any of the modules listed above within a circuit enabling the user to perform TCAD on complex systems of devices and passive elements. This feature leads to large-signal analysis which will include both time-domain and harmonic balance techniques.

 

Figure 5. Current - driven DC-IV simulation illustrating the efficient
extraction algorithm, where samples are only taken in regions of change.

Features

One method of the optimizations has been to modify the ATLAS code from a "voltage driven" format, where the terminal biases are applied, to a "mixed current/voltage driven" form, where the input (source) current and gate bias are specified and used to calculate the corresponding drain bias and gate current. This new approach allows FastATLAS to reduce simulation times by an order of magnitude. Unfortunately if a solution at a specified drain bias is desired this must be found using ireation on the drain current, somewhat reducing the gains in efficiency. However, importantly, if a DC-IV sweep is performed the simulator can be left in "current-driven" mode and no iteration is necessary. In fact an automatic DC-IV generation algorithm has been written that increases the efficiency of the whole simulation since it is able take large steps in the linear regions of device operation and only refines the output in areas of change, in particular around the "knee" of the IV curve and at breakdown. The results can then be interpolated onto individual drain bias positions, with accuracy guaranteed by the tolerance entered into the generation algorithm. Typical results are displayed in Figure 5 illustrating the clustering around the knee and larger steps in the ohmic region of device operation and as the device goes into saturation. The interpolated results taken from this curve have less than 0.003% error compared with the full voltage-driven results and were completed in less than 4% of the time.

Transport options include conventional drift-diffusion and hydrodynamic energy balance, with a range of different mobility and energy relaxation models. An additional feature available in FastATLAS is the transport parameter database. A new set of models have been developed using three valley ensemble Monte Carlo simulation to derive the carrier mobility, velocity, effective mass and both the energy and momentum relaxation times as functions of electric field, doping and ambient lattice temperature. Figure 6 illustrates the variation of carrier velocity as a function of field and doping in GaAs where velocity overshoot and saturation are clearly visible. Further, due to the new automated solution process the simulation convergence is relatively independent of transport models. FastATLAS works within the VWF framework, and is interfaced to all SILVACO input and graphical analysis tools. Figure 7 displays the conduction band energy of a recessed GaAs MESFET biased at 2 volts Drain-Source, and volts on the gate.

 

 

Figure 6. Carrier velocity as a function of electric field (V.m-1)
and doping density (m-3). Generated using a 3
valley ensemble Monte Carlo model.

 

Figure 7. Conduction band profile generated by FastATLAS
for a 1/2 micron gate MESFET biased at 2 volts VDS.

 

 

Conclusion

FastATLAS is a new and highly efficient TCAD tool for arbitrary, non-planar MESFET and HEMT device simulation. New techniques allow automated mesh generation, bias step control and very high frequency analysis. Device optimization can be done using the most advanced physical model with almost no speed penalty. A 1000x to 10000x speed up over conventional device simulation allows results to be obtained in seconds.