Device Level Simulation Challenges for DSM Mixed Signal Design

Pallab Chatterjee - President, P&D Engineering Consultants, Inc.

As a mixed signal circuit designer, the availability and applicability of tools for use in Deep Submicron circuit design, leaves a lot to be desired. There are several challenges facing the designer in arena. A few of these are: Performance aspects of SPICE type simulators, ability to get accurate and application region representative "analog" models from "digital" wafer foundry suppliers, tool set commonality across multiple platforms and multiple clients and data set reuse on previously developed intellectual property (IP).

A solution to some of these issues can be found in the SmartSpice program, as opposed to HSPICE™, PSPICE™, and Spectre™. I will recount a recent design experience that indicated how SmartSpice solved a number of problems that would not be resolved with the other tools.

The design targets for the block in question is a fairly straight forward Unity Gain stable 400MHz+ CMOS only amp, with a common mode range of 1.5v to 3.5V, power supply of 5.0v, and sub 10ns settling time. The process is a standard single poly 3 metal 0.5µm N-well flow, with diffusion caps and poly resistors. The devices have a nominal Vt of ~0.8v. The design environment was initially HSPICE™ based for device model libraries (level 28 & 49) and use a design library based on PSPICE™ design libraries.

The design flow began by converting the baseline PSPICE™ library data to HSPICE™ library format. This conversion included the reassimilation of the legacy data libraries in HSPICE™ to verify that the design conversion was completed correctly. (Note: This effort was not accounted for in the original schedule). After the base libraries were converted, the new design process could start.

Initially, the design was started by looking for a DC operating bias condition that also met the high level transfer function (.TF statement) criteria for the application. The sub-micron Level28 models had significant difficulty finding valid solutions on what were scaled version of known good designs. Additionally, the temperature and process spread effects seemed to not behave properly as "traditional" engineering variations. This was the first indication of a modeling and tool problem.

We then progressed the design process to the AC analysis stage, and found inconsistencies in the reported gains and impedances of devices between the AC and DC models - even if the SAVEBIAS and NODESET options were enabled to give the same starting conditions. The DC figures made sense based on previous designs, but the AC results were not correct - they indicated 5%+ deviations in gain figures. These results were greater than 10% deviation for open loop conditions. The phase plots indicated that the design was marginally stable at 40-45 of phase margin in typical models and as low as 25 at the process corners.

The transient analysis (closed loop only) indicated a stable operating condition with a standard critically damped response (sub 10ns settling time) for a nominal 27MHz 1Volt step function input. This result, although expected based on paper design analysis, was unexpected based on the results of the AC analysis. If the AC results were correct, the design should have exhibited significant damped ringing or gone into uncontrolled oscillations due to the limited phase margin and the high bandwidth input signal.

Neither of these anticipated outputs was found. The circuits had moderate difficulty finding an initial solution for either the fast or slow process corners.

A simplified schematic of the amplifier core design is shown in Figure 1. The results for the closed loop amplifier configuration (vdb, vp and vt) is also shown.

 

Figure 1. Simplified schematic of amplifier core.

 

These curves clearly show that the device has a marginal unity stability based on the peaking of the gain curve (~8db) which starts at ~100MHz and goes until ~1.2GHz. This is not consistent with the transient analysis which shows well behaved responses until ~400MHz.

The HSPICEtm results were fairly inconclusive and did not indicate a high degree of confidence on a design that was just a process scaling of a known good cell. After informing the wafer fab that we believed there was a modeling problem, they informed us that BSIM3V3 models were available, for SpectreTM only, which would give us better results. However, as a small design group, we did not want to support yet another simulator package that has its own file/library format and special model requirements.

After we received and reviewed the new models, it indicated that the BSIM3V3 models were created and curve fit using UTMOST. Since the models were optimized by UTMOST, it implicit indicates that the models were optimized and will run on SmartSpice.

The use of SmartSpice fits well into our current methodology that is heavily based on design reuse. For due diligence on the new models, the existing PSPICE(tm) libraries were run on SmartSpice to verify the design targets and simulator convergence. The PSPICE(tm) libraries and circuit files ran with no problems and no modifications required. The only modification that was required was the change of the Spectre(tm) model LEVEL from 11 to 49.

 

Figure 2. HSPICETM AC analysis results.

 

After the results for the original PSPICE(tm) models were obtained, we attached the current circuit design which had HSPICE(tm) control files. The HSPICE(tm) circuit files ran on the SmartSpice software with out any modification (other than updating paths). The results of the SmartSpice runs were interesting. They identified a gain consistency (to the 5th decimal place) on the DC and AC analysis. Further, they indicated a UGBW of greater than 2GHz, which was anticipated in the paper/hand calculation design and is supported by the transient response.

The transient response showed settling is sub 8ns in a very stable amplifier. There was no difficulty in finding the initial transient solution at typical, fast, or slow models. The devices also behaved properly with temperature skews. Figure 3 shows the unity gain configuration AC analysis which exhibits a sub 3db peaking and a larger phase margin.

 

Figure 3. SmartSpice AC analysis results.

 

The results from SmartSpice are accurate, fast, consistent (between DC, AC, and Transient analysis) and easy to review with the flexibility of the graphic post-processor. The ease of use on the product is excellent based on the fact that there is no code translation or learning curve required before utilizing existing design data. For DSM and general mixed signal design it is the preferred device level simulation tool as it allows for maximal use of historical/reference designs as well as schematic capture/netlist to simulation flows for new designs.