Blaze Simulation of SiGe:Si Heterostructure p-MOSFETs

P. A. Clifton, and A. G. O'Neill*
*Department of Electrical and Electronic Engineering, University of Newcastle, UK.

 

Introduction

The 2-D heterostructure device simulator Blaze is used here to investigate the design criteria for sub-micron p-channel SiGe:Si heterostructure MOSFETs. Thin layers of compressively strained SiGe grown 'pseudomorphically' on silicon substrates exhibit improved in-plane hole drift mobility relative to Si (800 cm2/V.s [1] c.f. 450 cm2/V.s) and may be applied in future enhanced p-channel devices (as shown schematically in Figure 1) for high performance CMOS. The use of a buried channel is also expected to improve carrier mobility and noise performance by reducing the interaction of carriers with the oxide interface. A major constraint on HMOSFET performance is the onset of parasitic inversion at the cap-oxide interface where carriers have degraded mobility. This limits the degree of inversion in the strained channel layer by electrostatic screening and hence degrades the small signal transconductance.

Figure 1. Schematic of the strained
SiGe p-channel heterostructure MOSFET.

Device Simulation

Numerical simulation based on Atlas-Blaze is used here to explore the design parameter space for enhancement (inversion) mode SiGe p-HMOSFETs. Fermi-Dirac statistics for carrier populations and a dense mesh specification for the thin epitaxial layers are required for accurate modeling of charge distributions and drift-diffusion based current formulations have been found to be sufficient for the range of channel lengths investigated (down to 0.25um).

The epitaxial cap and channel layers in the simple device structure are assumed to have low background doping (5x1013 cm-3) and the underlying substrate (or n-well) uniformly doped to varying degrees (Nsub cm-3) in the range 1x1016 cm-3 to 5x1017 cm-3. Interface states are neglected, a p+ polysilicon gate is used and the threshold voltage is allowed to shift freely according to channel doping and layer thicknesses.

D.C. output characteristics and small signal transconductance have been obtained (the latter by AC analysis [2]) and the respective inversion layer carrier populations in the cap and channel have been extracted by integrating the carrier profiles across the total depths of these layers. The region of integration was defined midway between source and drain at zero drain bias so as to avoid the complicating effect of junction depletion regions.

 

Density of States in Strained Layers

A reduced effective density of states (DOS) in the valence band, NV , is inherent in the use of compressively strained SiGe channels on Si [3], being intimately linked to the enhanced hole mobility [4,5]. The lower density of states effective hole mass and the reduced carrier scattering due to the lifting of the valence band degeneracy are both thought to contribute to higher uh. As the Ge fraction in a strained SiGe layer, x, is increased, NV , is predicted to fall monotonically [5] - by a factor of 5.6 at x=0.3, an effect that should not be ignored in modeling HMOSFETs.

 

Benchmarking

An experimental 0.7 micron channel length SiGe p-channel MOSFET reported by Nayak et. al. [6] has been used as a benchmark to support the validity of the simulation results. In modeling this device, which had a SiGe composition factor x=0.2, the effective NV , in the SiGe channel layer was reduced from 3.09x1019 cm-3 to 7.09x1018 cm-3 according to [5] and the band offset was taken as 0.15eV based on the mean of the reported values collated in [7]. The carrier mobility in the surface channel was assumed to be degraded with increasing transverse and longitudinal fields using the 'CVT' model [8] and the mobility in the SiGe channel was assumed to be insensitive to the transverse field. By using only the layer mobility values as fitting parameters (mh =185 cm2/V.s in the SiGe and mh(max)=255 cm2/V.s in the Si cap), a good fit to the experimental transconductance curves has been obtained, as shown in Figure 2(a). Extracted inversion layer carrier concentrations, shown in Figure 2(b), indicate that the level of inversion in the SiGe channel is in fact very low in these devices and that the main contribution to the drain current comes from the undesirable surface inversion layer in the silicon cap.

The effect of a reduced density of states on the carrier concentration in the strained channel is marked, as shown in Figure 2(b), where the saturated carrier concentration falls from 1.19x1012 cm-2 to 0.83x1012 cm-2 when NV in the SiGe is reduced by strain from 3.09x1019 cm-3 to 7.09 X 1018 cm-3. Neglecting the reduction in NV is liable to lead to falsely low extracted hole mobilities in experimental devices due to overestimation of carrier concentrations in the SiGe channel.

Figure 2.

(a) Transconductance curves obtained by simulation using the fitted model
for a 0.7mm gate length p-HMOSFET. Upper curve is for device in
saturation (VDS=-2.5V) and lower curve is linear (VDS=-0.1V). The
dots represent the experimental data reported by Nayak et. al. [6].

(b) Surface and channel inversion layer hole concentrations obtained
for the same device, both with full (3.09x1019 cm-3, dotted lines) and
reduced (7.09x1018 cm-3, full lines) DOS in the strained SiGe.

 

 

Response Surface Methodology.

In order to thoroughly explore the large parameter space which determines the performance of a HMOSFET, the experimental 0.7um channel length device [6] has been taken as the basis for an investigation by response surface methodology (RSM), a feature of the VWF Automation Tools. The dependencies of the SiGe:Si valence band offset and the hole mobility on SiGe layer composition (x) were respectively modeled as ^EV = 0.75x eV [11] and uh(SiGe) = 750x cm2/V.s, a conservative assessment of hole mobility based on early literature values [6] [9] [10] for experimental devices. The drawn channel length was maintained at 0.7mm and NV in the SiGe was fitted to the data given in [5].

The same calibrated device model was used throughout and a 24 full factorial design based upon a body centered cubic structure was implemented with the four input factors; oxide thickness (tox ), cap layer thickness (tcap), substrate doping (Nox) and Ge composition in the channel (x). Previous (unreported) studies have shown that neither the channel thickness nor the presence of a spacer layer between the channel and the doped substrate play a significant part in the device performance and hence these factors are neglected here.

Three key output metrics have been modeled as functions of the four input factors: nch(max) - the maximum hole concentration achieved in the SiGe channel with VGS = -2.5V, ^VGS - the gate voltage range above the threshold voltage over which the integrated inversion charge in the SiGe exceeds that in the cap and gm(max) - the maximum transconductance obtained with VDS = -2.5V.

A wide range of functional relationships can be examined between each of the output factors and the four input factors, usually by the use of response surface plots. Selected cuts through the 4-dimensional factor space of the experiment are presented in figures 3 to 5 to illustrate major trends.

 

Discussion.

It may be seen in Figures 3-5 that all the metrics of device performance; nch(max), gm(max) and ^VGS generally deteriorate as the thickness of the cap layer is increased. This is particularly important at high substrate doping levels (Figure 3) which lead to strong band bending (high transverse field) in the channel region under gate bias. The threshold for parasitic surface inversion is consequently reduced relative to that for SiGe channel inversion, so causing ^VGS to decrease. A smaller useful range ^VGS is concomitant with reduced SiGe inversion charge and hence smaller transconductance. In Figure 4, gm(max) can be seen to fall as tcap and Nsub increase. The use of a large value of band offset (high x) improves ^VGS markedly, as expected (Figure 5), since the threshold voltage for inversion of the buried channel is reduced relative to that of the surface channel. It is important to note that the role of the band offset is not so much in providing carrier confinement in the strained SiGe as in allowing an inversion layer to be induced in the SiGe rather than at the oxide interface. That is, a smaller offset does not degrade performance by allowing carriers to leak out of the SiGe potential well but rather it reduces the critical bias range ^VGS.

Figure 3. RSM results obtained for the
device represented in Figure 2.

 

Figure 4. RSM results obtained for
the device represented in Figure 2.

 

A thinner gate oxide also results in a higher nch(max) (not shown) and hence improves current drive and gm(max) due to the improved capacitive coupling between gate and channel charges. These improvements in performance will always overcome the disadvantage of the small reduction in ^VGS arising with the thinner oxide which is evident in comparing Figures 5(a) and (b).

Figure 5. RSM results obtained for
the device represented in Figure 2.

 

Deep Sub-micron HMOSFETs.

It has been seen that the main limitations on HMOSFET operation arise at high levels of sub-channel doping, i.e. under the conditions associated with deep sub-micron devices. A great benefit of RSM is that any combination of input factors (within the modeled parameter space) may be inserted into the derived empirical RS model to determine a good estimation of the device performance. For example, taking a typical 0.35um MOSFET with Nsub = 4.5x1017 cm-3 and a 9nm thick oxide, negligible conduction in the SiGe channel is achieved for x=0.2 and the channel population is still rather limited for x=0.4 unless very thin cap layers are employed. Going a stage further to a 0.25um channel length p-HMOSFET with Nsub @ 5.5x1017 cm-3, ^VGS may diminish to zero (the surface inverts before the channel) even for a cap thickness as small as 7nm. This is illustrated by the simulation results shown in Figure 6 (d=0) for a device based on the one reported by Kesan et. al. [10] (^Ev=0.15eV). This device was simulated using the same numerical model as for the Nayak [6] HMOSFET but fitting values of 350 and 300cm2/V.s for the maximum channel and cap layer mobilities respectively. The graph of integrated sheet hole concentrations, Figure 6(b) (d=0), shows that this structure supports very little inversion charge in the buried SiGe channel. It is possible that the reported improvement over an equivalent conventional Si MOSFET may be largely attributable to the use of undoped silicon in the cap.

Figure 6.

(a) Transconductance curves obtained by simulation
for an experimental 0.25mm gate length
p-HMOSFET [9] with and without delta
doping (VDS=-2.5V). Dots represent experimental results.

(b) The inversion layer hole concentrations
without delta (d) doping layer (full line)
and with a d-dose of 0.8X1012 cm-2 (dotted).

 

Clearly, based on the foregoing results, the cap layer should be made as thin as possible. However, a minimum value may be determined by two primary limitations; avoidance of high interface state densities (a minimum thickness of Ge-free silicon of order 6nm may be required [11]) and the avoidance of remote carrier scattering (by the insulator-semiconductor interface). Some experimental evidence suggests the latter may require a cap layer thickness of the order of 10nm [12] [13]. To enable significant benefit to be gained from the use of buried strained layer channels in sub-micron MOSFETs, two options exist - increase the offset potential between the cap and channel layers or reduce the peak field in the semiconductor. Growth of the HMOSFETs on silicon-on-insulator (SIMOX) substrates is one approach to field reduction [14], but, because of the heightened technological demands, does not appear to be a near term solution. Modulation doping provides one alternative.

 

Pulsed Modulation Doping.

It has been shown experimentally that a 'pulse' or 'delta' doped acceptor layer in the spacer below (but in close proximity to) the SiGe channel allows the inversion layer carrier concentration in the SiGe to be increased [11] [15]. In addition, the pulse doping layer reduces the threshold voltage for inversion of the channel and increases ^VGS. Figure 6(a), shows that the inefficient device with a 7nm thick cap and effective gate length of 0.25um (Nsub of 5 X 1017 cm-3) is enhanced by the addition of 4nm thick pulse doping layers (of varying dose) set back 4nm below the channel. Peak transconductance improves from 144 mS/mm to 268 mS/mm and ^VGS from 0V to 0.4V as the sheet dose is raised from 0 to 2.0 X 1012 cm-2. This very significant increase in gm(max) demonstrates the improvement in performance possible through epitaxial growth capabilities, such as in-situ modulation doping, quite apart from gains achieved by further increasing mobility. A d-dose of 3.2x1012cm-2 increases gm to a value in excess of 400 mS/mm, remarkably high for any type of p-channel FET. Note that in this case, an n+ polysilicon gate is required to ensure enhancement mode operation (negative VT), in the same manner as for a conventional buried channel p-MOSFET.

The increase in ^VGS is largely due to the reduction in transverse field achieved by the presence of the fully depleted pulse doped layer. This effect is the same as that proposed in the use of a 'back junction' [16] to modify the transverse field but in this case, excessive source-drain leakage in the off state (not shown) is avoided as long as the pulse doped layer is fully depleted.

Summary

As MOSFET gate lengths are shrunk to deep sub-micron dimensions, dopant concentrations in the channel region are forced higher to suppress short channel effects (~6x1017 cm-3 and 1x1018 cm-3 for 0.25um and 0.12um channel lengths respectively). 2d device simulation shows that it becomes ever more difficult to ensure inversion of a buried channel layer in HMOSFET devices with these levels of (sub channel) doping. This trend must be offset by employing maximum offset potentials at the cap-channel interface and minimum cap layer thicknesses. The same argument applies to n-channel HMOSFETs based on strained Si layers on SiGe. In the limit, this would suggest the use of Si (n-) and Ge (p-) channels for CMOS based on a relaxed Si1-xGex (x=0.5) virtual substrate. Modulation doping using pulse doping layers below the strained channel is a useful approach to extending the range of gate voltage over which conduction along the strained channel dominates. Indeed, this may prove essential if improved current drive and transconductance are to be realized in ultra-small geometry devices.

This article is based on material to be published in Microelectronics Journal.

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