CLEVER - Process Technology Based Extraction and Optimization of Custom Cell Parasitics

Introduction

Silvaco has recently released a new suite of interconnect analysis tools to meet the demands of state of the art cell, circuit and chip design. Next generation IC's are now being designed with sub-0.25mm CMOS technology and submicron multi-level interconnect systems. It is becoming increasingly clear that this combination of advanced technologies requires accurate values for the parasitic R and C components. Without such considerations CAD engineers will face an almost impossible engineering task both today and in the near future.

Traditionally these parasitic components have been calculated based upon empirical models or at best two-dimensional device simulations. Both of these methods are now exhibiting questionable values as 3D fringing effects become severe and 3D layouts become more common. CLEVER has, at its fundamental core, an advanced fully 3D backend process simulator ODIN which is able to finally provide the solution CAD engineers have been waiting for.

This article will illustrate the application of CLEVER beginning from layout information, through 3D process simulation and finally extraction of the parasitics. As the subject for this study an exclusive NOR cell (EXNOR) design has been chosen. CLEVER will be required to produce a netlist of the parasitic capacitance, resistance and active devices. This netlist is automatically back annotated and therefore immediately available for analog circuit simulation.

A Layout-Driven Approach

The CLEVER design phase is centered around an easy to use GUI designed to allow efficient data handling and seamless integration of the individual tasks required for extraction (Figure 3).

The starting point for CLEVER analyses is to import a GDSII file into the MASKVIEWS layout editor where the designer may save the entire cell or choose a portion of the cell for the analysis. In this application the entire EXNOR cell in Figure 2 will be analyzed.

 

Figure 2. Original GDS-II layout of exclusive NOR cell
Node labels are read from GDS-II file.

 

Figure 3. A file manager stores and organizes
inputs and results from CLEVER.

 

 

3D Process Simulation

In any advanced custom cell, such as in Figure 2, there will be many areas of prime importance. These could include linewidth variations, corner rounding, non-uniform etch rates and lithographic effects. Four major types of structure which CLEVER can handle are

  1. manhattan structures where etching results in ideal rectangular block shapes
  2. non-manhattan structures that exhibit the effects of isotropic etching
  3. lithographic effects where etching depends on the photoresist exposure
  4. multi-metal interconnects with multiple dielectrics

CLEVER uses the 3D process simulator ODIN designed to allow all these variables to be taken into account inside a single custom cell. This was achieved by linking layout information generated from MASKVIEWS to the process information required by ODIN. For the purposes of this article the EXNOR design has been performed for a non-manhattan structure as shown in Figure 1.

Figure 1. Accurate parasitic extraction for an
exclusive NOR cell requires realistic
interconnect geometries.

 

 

An additional underlying rule was that the 3D tool should remain usable for engineers with little TCAD experience. Therefore the amount of information required in the process input deck has been made as minimal as possible. This has been helped by the development of a proprietary 3D tetrahedral based, adaptive meshing algorithm that results in virtually no user intervention. A benefit from this is that the number of mesh points required is minimal as can be seen by the mesh shown in Figure 4.

 

Figure 4. The 3D adaptive meshing in CLEVER
requires no user intervention beyond specifying
the desired accuracy of the final parasitics.

 

The 3D process simulation capabilities are technology independent and support multiple dielectrics, arbitrary metals and polysilicon.

 

3D Parasitic Extraction

The field solver within CLEVER allows the calculation of the resistance and capacitance. In order to do this information must be provided to identify the active devices in the cell. This is accomplished with the aid of a technology file that applies Boolean logic to the mask layers in order to identify the active areas.

CLEVER extracts the active device connectivity. Active devices are saved to the netlist with width, length and other geometrical SPICE parameters. This will allow the correct junction capacitance in future spice simulations to be included automatically. Once identified they are removed from the electrical analysis. CLEVER will also introduce extra contact nodes into the layout in order to "split up" complicated metal paths so that a distributed RC spice netlist is obtained. These extra, or auxiliary, nodes are then back annotated onto the layout and can be viewed using MASKVIEWS. Figure 5 shows the new layout file obtained for the EXNOR under analysis.

The extracted parasitics are annotated into a netlist according to the node names in the GDSII file, although custom node names can be added using MASKVIEWS. A portion of the netlist generated for the EXNOR is shown in Figure 6.

 

Figure 5. EXNOR layout annotated with internal
node locations. The internal nodes are used for
back-annotation to the netlist.

 

Figure 6. Netlist produced by CLEVER includes
active devices as well as parasitics.
Back-annotation with original node labels is available.

 

 

SmartSpice Circuit Analysis

To illustrate the circuit performance obtained from CLEVER analysis three examples are studied - the EXNOR cell, an inverter cell and a buffer circuit. These will illustrate some typical uses of CLEVER.

The netlist produced from the CLEVER analysis of the EXNOR cell can be used to illustrate the dependence of interconnect and junction capacitance effects on the delay times, as shown in Figure 7. Using CLEVER engineers can optimize design parameters and immediately know the influence on circuit performance.

To take a simpler example, Figure 8 shows the layout of an inverter cell designed with NMOS and PMOS transistors. CLEVER has been used to analyze this cell under three processing conditions - manhattan, non-mahattan and lithographic etching. The extracted netlists have been used within a 9 stage ring oscillator circuit in order to show the effect on circuit performance. Figure 9 shows the influence of the processing conditions on the delay times and clearly illustrates the importance of obtaining accurate information on the parasitic components.

Finally, the effect of varying metal linewidths has been examined based upon the buffer circuit layout in Figure 10. Within the SmartSpice deck an inverter load has also been implemented. Figure 11 shows the effect of different metal linewidths, for the metal 2 layer, on the resultant delay times for this circuit.

 

Figure 7. SPICE simulation showing
the effect of interconnect parasitics on
timing of the EXNOR cell.

 

Figure 8. CMOS inverter layout used
to compare different interconnect geometry models.

 

Figure 9. Effect of using idealized geometries
vs. realistic interconnect process simulation
on ring oscillator gate delay.

 

Figure 10. Metal sepentine used to examine
metal width effects.

 

Figure 11. Effects of different metal
widths on inverter's gate delay are plotted.

 

Multi-Metal, Multi-Dielectric Structures

CLEVER can handle interconnect structures of arbitrary complexity. In modern processes a description of purely aluminum interconnects embedded in a homogeneous oxide dielectric is wholly inaccurate. The use of Tungsten plugs, anti-reflective coatings, low k dielectrics and copper interconnects are increasingly common. Extraction of resistance becomes a non-trivial problem in this case. Figure 13 shows an SRAM cell simulated with multiple metal materials. Since the metal interconnects are coated with liner and barrier layers, Figure 12 shows a 2D cross section of this structure for greater clarity. In addition to the multiple metal materials this cell also has 45 degree layout. The traditional 'counting squares' methods are insufficient for half-micron technology. Conductivities and permittivities of arbitrary materials are easily defined in the syntax of CLEVER. The netlist produced from this cell reflects the resistive effects of copper and tungsten.

 

Figure 12. 2D cross-section of SRAM
cell showing multiple metal materials.

 

Figure 13. SRAM cell with 4 metal layers
plus polysilicon. Each metal layer is composed
of multiple material layers which are
correctly modeled by CLEVER
for accurate resistance extraction.

Conclusion

Technology has reached the stage where engineers now require much more accurate information on the parasitic components within custom cells and their effects upon circuit performance. This can now only be achieved through the use of a fully 3D process simulator with an easy to use user interface. This article has shown some of the basic operation of CLEVER and the types of analysis engineers will be capable of performing.

 

 

Silvaco International acknowledges the contributions of our development partner GRESSI during the development and test of CLEVER.