Simulation of Ferroelectric Materials
(FRAM Devices) in ATLAS

In recent years technology has progressed more in the area of DRAM memory cell technology than almost in any other chip technology. Each DRAM generation now exhibits increased chip size and shrinking cell size. However, a memory cell requires a minimum amount of charge to be stored in order to meet constraints such as signal-to-noise ratio, soft error rates etc. This has resulted in the original planar-capacitor DRAM becoming superseded by more and more complicated designs such as the high-capacity (Hi-C) DRAM, trench-capacitors, stacked gate structures and many more. The result is that DRAM processing is becoming three-dimensional and extremely complex. One suggested approach to reducing these problems is to use ferroelectric materials as the dielectric of the memory cell. Such materials offer dielectric constants 100-2000 times that of silicon dioxide dielectrics. Thus the required DRAM charge could be stored in either smaller geometry capacitors or allow DRAM manufacturing to revert to simpler planar processing. Additionally, ferroelectric materials can be electrically polarized and the state retained after the voltage condition is removed. As a result this material is of wide interest for use in nonvolatile memories.

Silvaco's two-dimensional device simulator ATLAS has been enhanced to allow the modeling of ferroelectric, or PZT, materials such as peroskite Pb(ZrxTi1-x)O3. Such a model requires the capability to define three very important phenomenon that are present in nearly all PZT materials

  1. user definable material constants to allow calibration to measured data
  2. electric field dependent permittivity
  3. polarization in ferroelectric materials and devices (hysteresis curves) resulting from the alignment of dipoles in the ferroelectric material

The model used to predict these effects is based upon work by Miller and McWhorter [1], who used simplified expressions to model polarization, but also takes into account the variation of the dielectric permittivity with electric field. The implementation into ATLAS is in the form of a "microscopic" model. This allows

  • arbitrary geometries and combinations of materials
  • compatibility with existing models (drift-diffusion, energy balance, mobility, recombination, etc)
  • product compatibility with S-Pisces, Blaze, Giga, TFT, Mixedmode
  • structure creation within either Atlas or Devedit
  • DC, transient and AC small signal analysis are all supported
  • traps, interface traps and interface charge can still be defined

To illustrate these points this article has initially chosen to simulate a typical MOS type capacitor structure shown in Figure1. The dielectric is defined as a region within Atlas and the ferroelectric properties are described on the model and material statements. Typical syntax within an input file to define a ferroelectric region could be


Figure 1. Simple one-dimensional ferroelectric capacitor for ATLAS device simulations.

models region=1 ferro

material region=1 ferro.eps=200 /
ferro.pr=0.5e6 ferro.ps=1e6 /
ferro.ec=2e4

A zero field relative permittivity of 200, a remnant and spontaneous polarization of 0.5e-6 and 1e-6 C/cm2 respectively and a critical electric field of 20 kV/cm have been defined. These are the user accessible parameters which define the characteristics of the ferroelectric material and may be used for calibration purposes.

Atlas can now be used to simulate a dc voltage sweep applied to the gate contact. By using the probe statement, the polarization and electric field at a point within the ferroelectric material can be saved to the logfile. By plotting the logfile data as in Figure2, a plot which relates the polarization to the electric field can be obtained. The coefficients used for the ferroelectric model have been optimized in this instance to match experimental values of polarization [2] and excellent agreement can be obtained, as shown. Figure 2 illustrates that not only can the polarization of the ferroelectric material be calculated but that Atlas can simulate the hysteresis properties found when the gate voltage is swept in different directions.


Figure 2. Comparison of measured polarization values to extracted values from an ATLAS simulation. This shows that ATLAS allows accurate simulation and reproduction of the hysteresis effect.

The ferroelectric model can also be used with ac small signal analysis to obtain the variation of the gate capacitance. Figure 3 illustrates the results of an ac small signal analysis that was carried out at each bias point of a dc gate voltage sweep. This analysis was carried out at a frequency of 1MHz. This result once again illustrates the hysteresis effect whereby the two curves are offset by a small gate voltage. In addition the effect of the electric field dependent permittivity is seen as an asymmetry in the capacitance curves around approximately 0V. By use of the probe statement it is possible to output the relative permittivity to the logfile during this simulation. Figure 4 shows the variation in the ferroelectric permittivity during the simulation. Both the calculation of the polarization and the capacitance of such a material is a key factor in the design of memory circuits [3].


Figure 3. Application of small signal AC analysis to simul.ate variation of capacitance with gate voltage . Both hysteresis and asymmetry effects are illustrated.


Figure 4. Variation of the ferroelectric permittivity with gate voltage, extracted from the previous experiment.

In more practical ferroelectric devices the PZT material would normally be "sandwiched" between layers of Titanium and silicon dioxide. Therefore it is important that Atlas can combine arbitrary materials with the PZT material. To illustrate this a more complicated and relevant application would be to simulate a two-dimensional ferroelectric FET. Atlas has been used to define this structure as shown in Figure 5 and a traditional threshold voltage simulation was performed. Once again this voltage was swept in both the positive and negative directions. Figure 6 plots the drain current variation versus gate bias for the ferroelectric material parameters as shown. A clear hysteresis effect can be seen, which is a consequence of the polarization of the ferroelectric material. This effect clearly produces a significant shift in the transistors threshold voltage. This result would suggest that the condition of having two possible drain current values for set terminal voltages could result in convergence problems. However, Atlas exhibits no such problems. Although it is advisable to perform the sweep with the initial condition of a negative gate voltage, increasing to a high gate voltage before returning to the initial condition. This is the standard case in practice, to ensure that the dipoles within the PZT material are initially aligned before the sweep commences, and should be done within the simulation in order to give an optimal fit to the measured data.


Figure 5. Two dimensional field-effect-transistor showing stacking of different dielectric materials within ATLAS.


Figure 6. Variation of drain current with gate voltage of the ferroelectric FET. The hysteresis effect in the ferroelectric polarization results in different threshold voltages depending upon the direction of the gate sweep.

References

[1] S.L.Miller and P.J.McWhorter, "Physics of the ferroelectric nonvolatile memory field effect transistor", J. Appl. Phys., 72(12), 1992, pp.5999-6010.

[2] S.L.Miller et al, "Device modeling of ferroelectric capacitors", J. Appl. Phys. 68(12), 1990, pp.6463-6471.

[3] F.K.Chai et al, "Effects of scaling thickness and niobium doping level on ferroelectric thin film capacitor memory operation", IEDM Tech. Dig., 1995, pp.123-126.