Simulation of Device Characteristics for a Silicon-On-Insulator MOSFET Device

This example illustrates the simulation of a short channel silicon-on-insulator (SOI) MOSFET by a nonisothermal solution to the energy balance equations. Silvaco's device simulator ATLAS allows a self-consistent solution of all six equations - Poisson's equation, the continuity equations, the energy balance equations for holes and electrons, and the lattice heat flow equation. As a result all physical models such as mobility and impact ionization have now been made energy dependent. This allows effects such as velocity over shoot to be accurately described and also properly takes into account physically non-localized phenomena such as impact ionization.

As a consequence of a "floating potential" region SOI device simulation has always presented a computationally very time expensive problem due to the slow convergence of the semiconductor equations. Indeed this problem is often aggravated by the effects of high field models, such as impact ionization, which must be included in the device simulation to model SOI phenomena.

This example has used ATLAS to create an n-channel SOI MOSFET with agate length of 0.8 µm and a silicon film thickness of 0.16 µm, as shown in Figure 1. In this device the silicon film has been doped to obtain a threshold voltage of 0.6V. Nonisothermal simulation requires that a thermal boundary condition be applied to the structure. In this case the thermal boundary condition was applied to the substrate contact which was forced to remain at 300 K.

Figure 1

Figure 1. Structure of the SOI MOSFET simulated in this example.

ATLAS was used to generate the standard plot of drain current vs drain voltage, for three gate voltages, as shown in Figure 2. These curves illustrate three common SOI phenomena which are important for design engineers- a "kink" effect, breakdown at a relatively low drain voltage and a negative differential resistance at high gate voltage. This shows that ATLAS can accurately take account of the biasing of the floating body, the parasitic bipolar action and the elevation of the silicon temperature at high gate voltage.

Figure 2. Simulated variation of drain current with drain voltage for three gate voltages.

As a result of the low thermal conductivity of the buried oxide the temperature of the silicon film can increase significantly. This change in temperature is an important design consideration. ATLAS automatically saves the maximum temperature found within the structure at each bias condition which can then be plotted as shown in Figure 3. Also, by saving the structure at a particular bias condition ATLAS allows the two-dimensional temperature distribution to be saved. Figure 4 shows a typical plot where the maximum temperature is shown to be generated at the drain junction.

Figure 3. Dependence of maximum lattice temperature on drain voltage at three gate voltages.

Figure 4. Two-dimensional distribution of temperature in the SOI MOSFET.

A simulation such as this contains the most time consuming numerical issues: a dense grid, 6 equations, an ill conditioned problem and a large number of bias steps. Such a simulation can take a significant amount of time even when executed on todays high speed cpu computers. Figure 5 illustrates the increase in speed for this simulation as the number of processors used by parallel ATLAS is increased.

Figure 5. Execution time improvement with number of processors for non-isothermal SOI simulation.

Besides standard dc characteristics it is often necessary to design for operation at very high frequencies as this may influence the transistor design. One of the most typical methods of examining this is to design a ring oscillator circuit. Using the SOI structure in Figure 1 a 3-stage ring oscillator has been simulated within MIXEDMODE. This circuit was designed with a total of 6 MOS transistors - 3 to be simulated within ATLAS and 3 to be implemented as SPICE models. This simulation therefore implements three times the number of mesh points which yet further increases the solution time per iteration. Figure 6 shows the simulated variation in output voltage of the ring oscillator circuit as a function of time. Once again parallel ATLAS allows significant time savings similar to those shown in Figure 5. The need for a parallel version of ATLAS for use in SOI device and circuit simulations is therefore readily apparent.

Figure 6. MIXEDMODE simulation of a 3-stage ring oscillator circuit.