Simulation of Latch-up in an n-Channel IGBT

Insulated Gate Bipolar Transistors (IGBTs) are a difficult problem for TCAD engineers. The physical operation of these devices combines both that of a CMOS MOSFET and that of a bipolar transistor.

One of the major problems that results from this is in the design of an accurate mesh. For the region where CMOS type operation occurs it is necessary to have a very fine mesh underneath the gate in order to accurately calculate channel current. In the rest of the device the mesh is normally made much coarser. Despite this however the total number of mesh points in these simulations is often very high. A second problem is that these devices can operate with very high levels of current and as a result they can suffer from serious heating problems.Therefore it is necessary to couple the solution of the semiconductor equations with the lattice heat flow equation. The result of these problems is that total execution time is very high.

This example demonstrates how device simulation can model the latchup behavior of an n-channel IGBT. The device was created within ATLAS with the dimensions as shown in Figure 1. To take account of parasitic capacitance a 2mF capacitor is connected in parallel to the collector contact. Also, a thermal contact was specified to be along the collector contact, at the bottom of the device, and held at a constant 300 K.

Figure 1. Structure of the n-channel IGBT for simulation.

The simulation of the latchup phenomena in IGBTs can be achieved either in the dc or transient modes of operation. The dc method consists of two parts. Firstly the device simulator solves for 8V on the gate contact. Next the CURVETRACER algorithm is used to vary the collector voltage, whilst ensuring that the collector current continually increases. This produces the standard Ice vs Vce plot that is shown in Figure 2. As the collector voltage increases the rise in current through N2 causes a voltage drop in this region. This in turn begins to forward bias junction N2-P1 which then initiates latching of the IGBT. The variation in temperature within the device during this process can be important in its design. Figure 3 shows how the maximum temperature varies during latchup. Initially the temperature increases with the rise in collector current. However, once junction P1-N2 begins to conduct the current density within the device reduces and the temperature decreases. As collector current begins to increase again the current density also increases and the maximum temperature within the IGBT rises once more.

Figure 2. Simulated Ic - Vce characteristics showing latch-up

Figure 3. Simulated variation of maximum lattice temperature during latch-up

The transient simulation of latchup again consists of two parts. Firstly, with the gate grounded, the collector is ramped to 200V. Secondly, transient analysis is carried out where the gate voltage is linearly ramped to 8V with a rise time of 20nsec after which the device changes state with time. Figure 4 shows the results of this transient simulation. After 20nsec the collector is at 200V and the current has risen to just below 2e-5 A/mm. At this point the current flow is mainly along the channel, underneath the gate, as shown in Figure 5. However,this current causes a voltage drop along it's path and this gradually causes the junction N2P1 to begin to become forward biased. As this occurs the current flow lines spread across the device as shown in Figure 6 for t=1 usec. Eventually the transistor N2-P1-N3 becomes turned ON, positive feedback occurs through transistor P2-N2-P1 and the device rapidly changes to its latched high current state.

Figure 4. Variation of collector current during the transient simulation.

Figure 5. Location of current flowing through the IGBT at time t=20nsec.

Figure 6. Location of current flowing through the IGBt at time t=1usec.

Both the DC and transient simulations can take a significant amount of time. Figure 7 illustrates the increase in speed for the simulation shown in Figure 4, as the number of processors used by parallel ATLAS is increased.

Figure 7. Execution time improvement with
number of processors for IGBT latch-up simulation.