Comparing Worst-Case Models Generated by SPAYN to Models Derived Using Traditional Methods

 

Introduction

This article will demonstrate how worst-case models are generated using SPAYN. These models will be validated using measured device characteristics. More traditional worst-case model generation methods will then be assessed and their results will be compared with those obtained using SPAYN. The SPICE model used in this work was the BSIM3 model.

 

Generation of Worst-Case Models Using SPAYN

Approximately 100 NMOS and PMOS BSIM3 models were extracted from a 0.6mm CMOS process. The models were read into SPAYN where automatic data filtering techniques were used to eliminate outliers and thus reduce the model sample size to 94 qualified parameter sets. Parameter means, standard deviations, maximums, minimums, ...etc..., were calculated and histograms were created. Some of the histograms which were produced are shown in Figure 1. Parameter corrections were also investigated and some scatter plots showing some correlated and uncorrelated parameter pairs are shown in Figure 2. SPAYN also calculated the parameter correlation matrix. The NMOS correlation matrix is displayed in Figure 3 and it can be seen that there are some significant parameter correlations present for the data under analysis.

 

Figure 1. Histograms of selected BSIM3 NMOS and PMOS parameters created by SPAYN.

 

Figure 2. Scatter plots of selected BSIM3 parameter pairs generated by SPAYN.

 

Figure 3. The SPAYN correlation matrix for the BSIM3 NMOS parameter set.

 

A SPAYN principal component analysis (PCA) was performed so that the independent dominant parameters could be identified. The PCA was applied to NMOS and PMOS parameters simultaneously so that the correlations between NMOS and PMOS parameters could be accounted for when the worst-case models were constructed. Three non-correlated dominant parameters were isolated and these were the NMOS low-field mobility (U0), the oxide thickness (TOX), and the PMOS zero-biased threshold voltage (VTH0). These sources of variation were traced back to variations in gate poly CD, gate oxide thickness, and the threshold voltage adjust implant. SPAYN constructed equations which related all of the non-dominant parameters to the dominant parameter subset. In any worst-case experimentation the dominant parameters were varied independently and the remaining parameters were determined using the derived system of equations. In this way the parameter correlations among the NMOS parameters, among the PMOS parameters, and between the parameters of both polarities were correctly recreated when SPAYN constructed a model.

SPAYN allows the user to manipulate the dominant parameters independently during any statistical model generation procedure performed. Properly correlated process corner, user-defined, or Monte Carlo model parameter sets can be constructed based on these dominant parameters. Worst-case model parameter sets can then be identified from these models.

A total of eight process corner models can be constructed from the three dominant parameters. This corresponds to all combinations of these dominant parameters where these parameters are set to their +/-ns limits. The number of standard deviations used (n) is user-defined within SPAYN and a value of 3 was chosen for this example. For any circuit application the associated worst-case models can be identified from simulations performed with the process corner models. Thus, the SPAYN user has flexibility in the definition of the required worst-case models because it is not uncommon for a circuit designer to find that worst-case models suitable for the analysis on one circuit may be totally inadequate for use in other circuit applications. This fact will be demonstrated later in this article.

 

Worst-Case Model Example Using SPAYN

Device characteristics were measured and logged for the same wafer die that the BSIM3 parameters were extracted from. Certain NMOS device currents, transconductances, and output conductances were chosen. In this section we will look at how accurately SPAYN managed to predict the worst-case limits of some of these device characteristics. The characteristics under analysis here were (a) a linear region current at a bias of VDS = 0.1V, VGS = 5.0V, and VBS = -5.0V (ids_lin_n), (b) the transconductance for the same device bias (gm_lin_n), (c) a saturation region current at a bias of VDS = VGS = 5.0V, and VBS = -5.0V (ids_sat_n), and (d) the output conductance for this saturation region bias point (gds_sat_n). The device characteristics were measured from 1/0.6µm devices. A circuit simulator was linked to SPAYN and the process corner models were used for circuit simulations of the device characteristics under analysis. Worst-case models and device characteristics were then identified. The worst-case predictions for the characteristics under analysis are tabulated in Table 1 along with the relevant measured statistical information.

Ids_lin_n
(Amps)
gm_lin_n
(Mhos)
Ids_sat_n
(Amps)
gds_sat_n
(Mhos)
Measured Minimum 4.22e-5 9.33e-6 5.01e-4 6.46e-6
Measured Maximum 6.25e-5 1.12e-5 7.81e-4 1.32e-5
Measured Mean Measured 5.25e-5 1.04e-5 6.24e-4 8.30e-6
Standard Deviation 3.80e-6 3.21e-7 5.35e-5 1.26e-6
PCA WC Low 3.70e-5 8.80e-6 4.20e-4 5.20e-6
PCA WC High 7.30e-5 1.15e-5 8.80e-4 1.60e-5
PCA WC Range 3.60e-5 2.70e-6 4.60e-4 1.08e-5
PCA WC Range in measured 's 9.5 8.4 8.6 8.6

 

Comparing Worst-Case Models Generated by SPAYN to Models Derived Using Traditional Methods

 

Table 1. Worst-case results using the PCA dominant parameter approach in SPAYN.

 

 

The simulated worst-case levels were very accurate and the simulated ranges of device operation averaged at about 8.8 times the measured standard deviation. This resulted in very useful worst-case limits which were not overly conservative/pessimistic.

 

Worst-Case Models Using a More Traditional Method

A more traditional worst-case approach was then used to predict some worst-case device characteristic limits. In this approach the model parameters were set to their upper or lower 3 limits so as to maximize or minimize the device current. Parameter correlations were essentially ignored in this methodology. The results of using this procedure are shown in Table 2. These results are far more pessimistic than the results obtained using the SPAYN PCA-based technique. The simulated ranges of operation are from 11 to over 24 times the measured standard deviations for the device characteristics under analysis. Worst-case circuit simulations based on the used of these models would be far too pessimistic, and the circuit design task may have been made unnecessarily over-complicated. In this case the over-prediction of the worst-case limits was solely due to parameter correlations, such as those which are apparent in Figure 2, being ignored. In this example the parameter variabilities were known, but in many situations the parameter upper and lower limits are simply guessed based on a knowledge of their typical values. This could lead to situations where predicted worst-case limits are even worse then those appearing in Table 2. If the variabilities of sensitive model parameters are under estimated then it is possible that predicted worst-case limits may even be over-optimistic leading to under-predictions of statistical circuit performance spreads. This would be even more dangerous than if the predicted limits were over-predicted.

 

 

Ids_lin_n
(Amps)
gm_lin_n
(Mhos)
Ids_sat_n
(Amps)
gds_sat_n
(Mhos)
Measured Minimum 4.22e-5 9.33e-6 5.01e-4 6.46e-6
Measured Maximum 6.25e-5 1.12e-5 7.81e-4 1.32e-5
Measured Mean Measured 5.25e-5 1.04e-5 6.24e-4 8.30e-6
Standard Deviation 3.80e-6 3.21e-7 5.35e-5 1.26e-6
Traditional WC Low 3.20e-5 7.20e-6 3.90e-4 3.80e-6
Traditional WC High 8.40e-5 1.50e-5 9.80e-4 2.10e-5
Traditional WC Range 5.20e-5 7.80e-6 5.90e-4 1.72e-5
Trad. WC Range in meas.'s 13.7 24.3 11.0 13.6

Table 2. Worst-case results using a traditional approach in SPAYN.

 

Figure 4 to Figure 7 show plots of the measured histograms of the measured device characteristics in use here. The simulated worst-case limits for the PCA-based technique (PCA high and PCA low) and the more traditional approach (Trad. high and Trad. low) also indicated.

 

Figure 4. Histogram of measured NMOS linear
region current with worst-case limits shown.

 

 

Figure 5. Histogram of measured NMOS linear
region transconductance with worst-case limits.

 

 

Figure 6. Histogram of measured NMOS saturation
region current with worst-case limits.

 

 

Figure 7. Histogram of NMOS saturation region
output conductance with worst-case limits shown.

 

 

 

A Worst-Case Analysis Example Using a CMOS Inverter

Traditional worst-case analysis methods are also dangerous when it is assumed that a single pair of worst-case parameter sets will be suitable for all circuit design applications. This situation can be avoided by using SPAYN. Circuit simulators can be linked directly to SPAYN so that the effects of model parameter variations on any circuit performance can be examined. If the process corner models, generated by SPAYN, are used then the circuit designer should get very good predictions of statistical circuit performance spreads no matter what the circuit under analysis is. The dangers of using a single pair of model parameter sets to predict circuit performance variations are shown in Figure 8 and Figure 9. These figures show plots of predicted CMOS inverter transfer characteristics and supply current characteristics. The simulations were performed with the 8 process corner models which were derived from a SPAYN PCA applied to the combined NMOS and PMOS parameter sets. The simulated inverter transfer characteristics appear in Figure 8, and model sets 1 (xxxx) and 8 (oooo) were seen to predict the worst-case limits for the inverter trigger voltage. Assume that these models were chosen to be the worst-case parameter sets for this circuit. Figure 9 shows the process corner predictions for the supply current characteristics for the same inverter circuit. It can be seen that model sets 1 and 8 would predict totally unacceptable limits for this circuit characteristic. The real limits for this circuit performance are far wider than those predicted with model sets 1 and 8. This can be seen in Figure 9 where simulations with the process corner models are plotted. In situations where worst-case predictions for a critical circuit or subcircuit are required it is recommended that SPAYN is used to simulate the circuit using all process corner models. Worst-case models are sometimes derived on the basis of current drive or device speed. Worst-case models found in this way will often be unsuitable, for example, in circuit applications where device transconductance or output conductance considerations are important.

 

Figure 8. Simulated CMOS inverter transfer characteristics
using all SPAYN process corner models.

 

Figure 9. Simulated CMOS inverter supply current
characteristics using all process corner models.

 

 

Conclusions

This article compared a traditional worst-case approach to one of the methodologies which is available in SPAYN. BSIM3 parameter sets for NMOS and PMOS devices, measured on many wafer die, were used to predict the statistical spreads in certain device characteristics. A traditional worst-case approach and a PCA-based approach using SPAYN were used to predict the required worst-case limits. Comparisons between measured results and the predicted worst-case limits were used to demonstrate the superiority of the PCA approach. In addition, the dangers of assuming that worst-case models which were derived on the basis of a certain circuit or device performance are suitable for all other circuit applications were pointed out. Worst-case analyses utilizing the process corner models identified by SPAYN will help circuit designers to predict accurate worst-case limits for any circuit design application. Worst-case circuit analyses using SPAYN will account correctly for parameter correlations, parameter variations, and the differences between the circuit performances under analysis.