Extraction of Scalable Temperature-Independent BSIM3 (Version 3) and Philips Level 9 MOSFET Models Using UTMOST

Introduction

A methodology by which scalable MOSFET models, valid over a wide temperature range, can be extracted using the UTMOST parameter extraction tool will be detailed in this article. The BSIM3 Version 3 (BSIM3v3) and the Philips Level 9 (MM9) models were used in this work. Local optimization procedures were utilized in order to extract the scalable NMOS and PMOS model parameter sets. One of the objects of this work was to develop parameter extraction strategies which contained the correct blend of accuracy, simplicity, and speed. These procedures will be described for the two models in question. The effectiveness of the parameter extraction processes will be assessed and the accuracy of the two models will be compared for all of the device geometries and temperatures used. An UTMOST batch-mode implementation of the two parameter extraction strategies was also developed. Such an implementation would be important where the UTMOST user wants to completely automate the parameter extraction process. In this manner, both the model parameter extraction turn-around times and the degree of human intervention are minimized.

 

Experimental Data

The data used in this experiment was measured for NMOS and PMOS devices from a 0.5mm CMOS process. Characteristics were measured for ten device geometries of each polarity. The devices chosen had W/L drawn dimensions of 10/10, 10/5, 10/2, 10/1, 10/0.8, 10/0.6, 10/0.5, 3/10, 1/10, and 0.8/10µm. Measured I-V data was obtained using the UTMOST BSIM3 extraction routine at temperatures of 27C, 85C, and 125C. Four families of curves were stored for each device:

(a) IDS-VGS data for VDS = +/- 0.1V and VBS stepped between 0V and -/+ 2V
(b) IDS-VGS data for VDS = +/- 3.6V and VBS stepped between 0V and -/+ 2V
(c) IDS-VDS data for VBS = 0V and VGS stepped between VTH +/- 0.2V and +/- 3.6V
(d) IDS-VDS data for VBS = -/+ 2V and VGS stepped between VTH +/- 0.2V and +/- 3.6V

All of this data can be accessed by the UTMOST ALL_DC routines for use in global or local parameter optimization procedures. UTMOST local optimization strategies allow the UTMOST user to identify regions of data for parameter optimization very specifically using any combination of voltage limits, current and/or conductance limits, sweep numbers, and device i.d. identifiers.

 

BSIM3v3 Parameter Extraction

A total of ten local optimization strategies were implemented for the BSIM3v3 model for the extraction of a parameter set which would be valid over all geometries and temperatures in use. These local optimization strategies are detailed in Table 1. For the sake of simplicity, the individual steps within any given local optimization strategy are not described and neither are the specific optimization target voltage and current limits. The Data column of Table 1 references the families of measured characteristics mentioned above i.e. (a), (b), (c), or (d).

Strategy Name Steps Parameters Optimized Target Devices Used Data
vgs_large_bsim3 4 VTH0, U0, UA, UB, K1, K2, UC, NFACTOR, VOFF
IDS Large Device (a) T=27C
ivgs_warray_bsim3 3 WINT, K3, W0, K3B, DWB IDS W-array Devices (a) T=27C
ivgs_larray_bsim3 6 LINT, RDSW, DVT0, DVT1, NLX, DVT2, UA, UB, UC, U0, PRWG, NFACTOR, VOFF, CDSC, CDSCB, PRWB IDS L-array Devices (a) T=27
ivds_DC_bsim3 2 A0, AGS, A1, A2, VSAT IDS  L-array Devices (c) T=27
ivgs_@VDS_bsim3 1 DSUB, ETA0, ETAB, CDSCB IDS L-array Devices (b) T=27
ivds_gds_bsim3 3 PVAG, PCLM, PDIBLC1, PDIBLC2, ETA0, DROUT, PSCBE1, PSCBE2 gds L-array Devices (c) T=27
ivds_@VBS_bsim3 2 KETA, PDIBLCB, ETAB IDS L-array Device (d) T=27
ivds_warray_bsim3 2 B0, B1, A0, A1, A2, VSAT  IDS All Devices (c) T=27C
ivgs_bsim3_T 2 UTE, KT1, KTL, UA1, UB1, UC1, PRT, KT2 IDS L-array Devices (a) T=125
ivds_bsim3_T 1 AT IDS L-array Devices (c) T=125

Table 1. The BSIM3v3 Local Optimization Strategy.

 

 

The BSIM3v3 local optimization strategy outlined in Table 1 proved to be very effective. A total or 44 BSIM3v3 room temperature parameters were extracted and 9 BSIM3v3 temperature parameters were extracted. Table 2 lists some of the relevant BSIM3v3 errors between measured and simulated characteristics for the devices under test in the case of the NMOS devices. Errors are quoted for the linear region current and transconductance (5 substrate biases) as well as for the saturation region current and output conductance at zero and non-zero substrate biases. Table 3 gives the associated results for PMOS devices. The same local optimization strategy was utilized for both device polarities. The errors listed in Table 2 and Table 3 are average errors for the room temperature data. Errors for the linear-saturation region output conductance (gds) are tabulated for the L-array devices only (without the Large device) where errors associated with measurement resolution problems are negligible.

Device
(W/L)
Linear
(IDS)
Linear
(gm)
IDS-VDS
(VBS=0V)
GDS-VDS
(VBS=0V)
IDS-VDS
(VBS=-2V)
GDS-VDS
(VBS=-2V)
10/10 0.6% 2.5% 1.6% - 2.4% -
10/5 0.9% 2.2% 2.9% 20.8% 3.7% 15.7%
10/2 0.5% 1.8% 2.1% 17.0% 2.9% 14.1%
10/1 1.0% 2.3% 3.9% 16.5% 2.5% 14.3%
10/0.8 0.7% 2.6% 2.4% 16.1% 4.3% 13.4%
10/0.6 1.0% 4.4% 2.8% 14.3% 4.1% 12.4%
10/0.5 1.9% 5.8% 3.0% 11.3% 6.9% 13.8%
3/10 1.4% 2.2% 1.6% - 3.6% -
1/10 0.9% 2.5% 1.2% - 3.8% -
0.8/10 1.0% 3.3% 1.9% - 2.9% -

Table 2 . Average errors between measured and simulated characteristics
associated with the NMOS BSIM3v3 model at T=27C.

 

Device
(W/L)
Linear
(IDS)
Linear
(gm)
IDS-VDS
(VBS=0V)
GDS-VDS
(VBS=0V)
IDS-VDS
(VBS=+2V)
GDS-VDS
(VBS=+2V)
10/10 0.6% 1.3% 1.7% - 4.8% -
10/5 0.6% 1.7% 1.9% 9.0% 3.5% 12.3%
10/2 1.1% 1.7% 2.0% 9.9% 0.8% 12.4%
10/1 1.0% 1.8% 2.7% 11.7% 2.5% 17.2%
10/0.8 0.8% 2.1% 1.3% 10.1% 3.8% 12.5%
10/0.6 0.7% 2.9% 1.7% 10.2% 3.2% 10.2%
10/0.5 1.4% 3.55 2.0% 10.0% 4.2% 10.5%
3/10 1.2% 1.9% 1.5% - 5.3% -
1/10 0.9% 3.4% 0.7% - 4.7% -
0.8/10 0.9% 4.4% 1.1% - 4.4% -

Table 3. Average errors between measured and simulated characteristics
associated with the PMOS BSIM3v3 model at T=27C.

 

The BSIM3v3 local optimization strategy produced a very accurate scalable model as can be seen from the error numbers quoted in Table 2 and Table 3. Figure 1 to Figure 5 show measured and simulated IDS, gm, and gds plots for the PMOS devices using the BSIM3v3 model. Characteristics are shown in the subthreshold, linear, and saturation regions of device operation. To enhance the clarity of the plots in these figures it was necessary to reduce the number of devices viewed to six. The devices geometries included are the 10/10, 10/2, 10/0.8, 10/0.5, 3/10, and 0.8/10mm devices.

 

Figure 1. Measured (____) and simulated (-----) PMOS IDS-VGS characteristics
where the BSIM3v3 model was used (VDS = -0.1V, T = 27C).

 

Figure 2. Measured (____) and simulated (-----) PMOS Log10 (IDS)-VGS characteristics
where the BSIM3v3 model was used (VDS = -0.1V, T = 27C).

 

Figure 3. Measured (____) and simulated (-----) PMOS gm-VGS characteristics
where the BSIM3v3 model was used (VDS = -0.1V, T = 27C).

 

Figure 4. Measured (____) and simulated (-----) PMOS IDS-VDS characteristics
where the BSIM3v3 model was used (VBS = 0.0V, T = 27C).

 

Figure 5. Measured (____) and simulated (---) PMOS gds-VDS characteristics
where the BSIM3v3 model was used (VBS = 0.0V, T = 27C).

MM9 Parameter Extraction

A total of ten local optimization strategies were also implemented for the MM9 model for the extraction of a parameter set which would be valid over all geometries and temperatures in use. These local optimization strategies are detailed in Table 4. Once again, for the sake of simplicity, the individual steps within any given local optimization strategy are not described and neither are the specific optimization target voltage and current limits.

 

Strategy Name Steps Parameters Optimized Target Devices Used Data
ivgs_refer_level9 4 VTOR, BETSQ, THE1R, KOR, KR, VSBXR, THE2R, MOR, ZET1R, ETAMR, VSBTR IDS Reference Device (a) T=27C
ivgs_warray_level9 5 WOT, SWVTO, SWTHE1, SWKO, SWK1, SWTHE2 IDS W-array Devices (a) T=27C
ivgs_larray_level9 7 LAP, SL2VTO, SLVTO, SLKO, SLK, SLVSBX, SLTHE1R, SLTHE2R, SLMO, SLZET1, BETSQ, ETAMR, VSBTR, SLVBST IDS L-array Devices (a) T=27C
ivds_prelim_level9 4 THE3R, SLTHE3R, SWTHE3 IDS L-array Devices (c) T=27C
rds_long_level9 1 VPR gds Large Device (c) T=27C
ivgs_@VDS_level9 2 GAMOOR, SLGAMOO, ETAGAMR, VSBTR, SLVSBT IDS L-array Devices (b) T=27C
rds_larray_level9 3 GAMOOR, SLGAMOO, VPR, ALPR, GAM1R, ETADSR, SLGAM1, SLALP, A1R, A2R, A3R, SLA1, SLA2, SLA3 gds L-array Devices (c) T=27C
ivds_all_level9 1 THE3R, SLTHE3R, SWTHE3 IDS All Devices (c) T=27C
ivgs_level9_T 5 STVTO, ETABET, STTHE1R, STLTHE1, STTHE2R, STMO, STLTHE2 IDS L-array Devices (a) T=125C
ivds_level9_T 1 STTHE3R IDS L-array Devices (c) T=125C

Table 4. The MM9 Local Optimization Strategy.

 

 

The MM9 local optimization strategy outlined in Table 4 also proved to be very effective. A total or 44 MM9 room temperature parameters were extracted and 8 MM9 temperature parameters were extracted. Table 5 lists some of the relevant MM9 errors between measured and simulated characteristics for the NMOS devices under test. Table 6 gives the associated results for PMOS devices. The same local optimization strategy was utilized for both device polarities.

 

Device
(W/L)
(W/L)
Linear
(IDS)
Linear
(gm)
IDS-VDS
(VBS=0V)
GDS-VDS
(VBS=0V)
IDS-VDS
(VBS=-2V)
GDS-VDS
(VBS=-2V)
10/10 1.7% 5.3% 3.9% - 8.2% -
10/5 1.0% 5.3% 4.2% 17.3% 5.8% 19.6%
10/2 1.1% 5.1% 2.7% 10.5% 5.5% 28.7%
10/1 0.8% 4.3% 2.4% 11.3% 3.5% 18.7%
10/0.8 0.8% 4.1% 2.0% 12.6% 2.7% 12.6%
10/0.6 1.1% 3.5% 2.5% 13.5% 2.5% 12.9%
10/0.5 2.2% 3.3% 3.0% 12.3% 5.0% 22.8%
3/10 1.3% 4.5% 4.4% - 4.9% -
1/10 1.6% 4.3% 6.1% - 7.3% -
0.8/10 1.4% 4.2% 6.2% - 7.7% -

Table 5. Average errors between measured and simulated
characteristics associated with the NMOS MM9 model at T=27C.

 

Device
(W/L)
Linear
(IDS)
Linear
(gm)
IDS-VDS
(VBS=0V)
GDS-VDS
(VBS=0V)
IDS-VDS
(VBS=+2V)
GDS-VDS
(VBS=+2V)
10/10 1.1% 2.1% 3.7% - 8.2% -
10/5 1.0% 2.4% 3.6% 23.5% 8.3% 25.2%
10/2 2.2% 2.0% 3.6% 21.6% 6.4% 26.2%
10/1 1.0% 1.9% 3.8% 18.8% 4.8% 22.6%
10/0.8 2.2% 2.6% 3.2% 18.3% 2.9% 18.3%
10/0.6 1.0% 2.2% 3.4% 14.8% 5.3% 19.0%
10/0.5 1.2% 2.4% 3.3% 12.1% 7.1% 19.7%
3/10 1.7% 1.8% 4.8% - 8.3% -
1/10 1.2% 1.9% 4.6% - 8.0% -
0.8/10 0.8% 2.0% 4.4% - 9.5% -

Table 6. Average errors between measured and simulated characteristics
associated with the PMOS MM9 model at T=27C.

 

As in the case of the BSIM3v3 experiment the MM9 local optimization strategy produced a very accurate scalable model as can be seen from the error numbers quoted in Table 5 and Table 6. Figure 6 to Figure 10 show measured and simulated IDS, gm, and gds plots for the NMOS devices for the MM9 model. Characteristics are shown in the sub threshold, linear, and saturation regions of device operation.

 

Figure 6. Measured (____) and simulated (-----) NMOS IDS-VGS characteristics
where the MM9 model was used (VDS = 0.1V, T = 27C).

 

Figure 7. Measured (____) and simulated (-----) NMOS Log10(IDS)-VGS characteristics
where the MM9 model was used (VDS = 0.1V, T = 27C).

 

Figure 8. Measured (____) and simulated (-----) NMOS gm-VGS characteristics
where the MM9 model was used (VDS = 0.1V, T = 27C).

 

Figure 9. Measured (____) and simulated (-----) NMOS IDS-VDS characteristics
where the MM9 model was used (VBS = 0.0V, T = 27C).

 

Figure 10. Measured (___) and simulated (-----) NMOS gds-VDS characteristics
where the MM9 model was used (VBS = 0.0V, T = 27C).

Model Comparison

Both the BSIM3v3 and MM9 local optimization strategies produced scalable models which were accurate over the device geometries tested and the temperatures imposed. The performance of neither of the models degraded significantly over the temperature range tested as can be seen in Table 7.

 

Model Polarity Temp. IDS_LIN gm_LIN IDS_SAT GDS_SAT
BSIM3v3 N 27C 1.0% 3.0% 2.3% 16.0%
BSIM3v3 N 85C 1.3% 2.8% 2.8% 16.1%
BSIM3v3 N 125C 1.3% 2.9% 2.9% 16.9%
MM9 N 27C 1.3% 4.4% 3.7% 12.9%
MM9 N 85C 1.4% 3.2% 3.5% 11.2%
MM9 N 125C 1.4% 3.4% 3.3% 14.1%
BSIM3v3 P 27C 0.9% 2.5% 1.7% 10.1%
BSIM3v3 P 85C 0.9% 2.4% 2.3% 13.1%
BSIM3v3 P 125C 1.0% 3.3% 2.8% 15.7%
MM9 P 27C 1.3% 2.1% 3.8% 18.2%
MM9 P 85C 1.0% 2.0% 3.8% 18.4%
MM9 P 125C 1.0% 2.1% 3.7% 18.7%

Table 7. Error values (averaged over all devices) for the BSIM3v3
and MM9 models for the three temperatures used.

 

 

Table 7 contains errors, averaged over all ten devices used, for linear region current, linear region transconductance, strong-inversion linear-to-saturation region current (VBS=0V), and strong-inversion linear-to-saturation region output conductance. Errors are quoted for both models, both polarities, and for all three temperatures. The linear region performance of both models was similar. MM9 lacked a second-order mobility degradation parameter which led to poorer fits than BSIM3v3 at high VGS biases for devices with large drawn lengths. MM9 seemed to model the moderate-inversion region better than the BSIM3v3 model. The average saturation region errors in device current were somewhat larger for MM9 than for BSIM3v3. This was due to the fact that BSIM3v3 was more successful in modeling narrow devices in this region of operation than MM9 was. MM9 produced very impressive predictions of saturation region output conductance for NMOS devices but this was not true for PMOS devices. The BSIM3v3 model was much more successful in modeling these PMOS characteristics and this seemed to be due to that fact that the BSIM3v3 model handled the modeling of the PMOS linear-saturation transition region better than the MM9 model. Finally, it was also noted that BSIM3v3 performed better in the modeling of saturation region current and output conductance for non-zero substrate biases than the MM9 model did. This was due to the fact the BSIM3v3 had parameters which could be adjusted to fit these characteristics whereas MM9 did not. All things considered, it must be said that both models yielded very acceptable scalable model solutions without any detectable discontinuities.

 

Batch-Mode Implementation

Batch-mode UTMOST command files were prepared in order to automate the BSIM3v3 and MM9 extractions described in this article. An example of one such command file is shown in Figure 11. These commands can be run from the VYPER environment or simply from the command line of a terminal window.The example shown in Figure 11 simply reads an UTMOST setup file containing the local optimization procedures, reads the measured data, sets up the appropriate devices for the selected UTMOST routines, performs the complete extraction, and stores the resultant BSIM3v3 NMOS model in a SPICE library format file. The equivalent MM9 batch-mode implementation is almost identical in appearance.

 

Figure 11. UTMOST batch-mode commands for the automatic
execution of the BSIM3v3 NMOS local optimization strategies.

Conclusions

This article describes methodologies by which scalable BSIM3v3 and MM9 parameter sets can be extracted using user-defined UTMOST local optimization strategies. Data from a 0.5mm CMOS process is used to bench-mark both the models and the extraction procedures. It was shown that the use of either model enabled the extraction of an accurate scalable model. An analysis of the two models over various temperatures also yielded encouraging results. Furthermore it was shown that the task of extracting an accurate scalable model could be automated using the batch-mode UTMOST environment.

 

Acknowledgement

Silvaco would like to acknowledge Yuhua Cheng of U.C. Berkeley, Dick Klaassen of Philips Research, Chris Lyons of Analog Devices and Kevin McCarthy of the NMRC for their contributions to this work.