Statistical Parameter Analysis for a Process Under Development Using SPAYN

Introduction

The importance of maintaining accurate worst-case SPICE models for existing, and nominally stable, IC manufacturing processes is well

understood. However, more recently there has been increasing pressure on IC manufacturers to provide worst-case SPICE models for processes under development, often in the absence of any fabricated wafers. This article will describe how worst-case BSIM3 MOSFET models were derived for a 0.6um CMOS process using an integrated environment comprised of process simulation, device simulation, parameter extraction, statistical analysis, and circuit simulation tools. The process simulation, device simulation and parameter extraction tasks were incorporated into the automatic Virtual Wafer Fab (VWF) framework. Mask variations, such as those which cause variations in effective device channel length, are typically too important to ignore and these are also programmable using the VWF. Previously, a task such as this would have required a large amount of user intervention which would have discouraged engineers from undertaking this important form of experiment. The goals of the work described in this article were (a) to devise useful "Rev. Zero" worst-case models for a process under development for use in circuit simulation, (b) to derive the important relationships which exist between the process variables and the BSIM3 model parameters, and (c) to use this information to examine the sensitivity of circuit performance to chosen process variables.

 

Experimental Description

Changes in specific process parameters and mask variations were defined using the VWF. A Monte Carlo experiment was constructed in which these process and mask variables were allowed to vary randomly according to Gaussian distributions with specific means and standard deviations. In this example, approximately 100 simulations were initiated. Each experimental split involved the automatic use of, and interaction between, the process simulation (ATHENA), device simulation (ATLAS), and parameter extraction (UTMOST) tools. Among the process and mask variables targeted for this analysis were the P-well implant dose, the N-well implant dose, the gate oxidation pressure, the threshold voltage adjust implant dose, and the polysilicon gate length delta CD. For each experimental split, ATHENA and ATLAS were used to create a set of I-V curves which were then used by UTMOST to derive a BSIM3 model parameter set for both NMOS and PMOS devices. At the end of the experiment the entire database of process and model parameters were loaded into SPAYN. SPAYN was used to perform the statistical parameter analysis and worst-case model generation.

 

Experimental Results

The inclusion of the UTMOST parameter extraction strategy into the VWF experiment was accomplished using the UTMOST batch-mode capability [1]. Figure 1 shows nominal measured (i.e. generated by ATLAS) I-V curves for NMOS and PMOS devices in addition to the associated SPICE simulated characteristics obtained as a result of an UTMOST BSIM3 parameter extraction. The device drawn width and length in this case were 1.0um and 0.6um respectively. Local optimization procedures were used to extract the BSIM3 parameters. The same parameter extraction procedure was applied to the device characteristics created by each of the process splits. The following information was logged to the VWF database:

  • the process variables which were varied as part of this experiment
  • some extracted process parameters i.e. TOX, VTH, Beta for each device.
  • the extracted BSIM3 NMOS and PMOS model parameters.
  • some selected I-V points which were generated by ATLAS and the associated extracted BSIM3 model i.e. measured and simulated Idsat.

When the entire experiment was complete, this parametric information was read into the SPAYN statistical analysis tool.

 

 

Figure 1. Nominal device simulation (____) and BSIM3
predicted (---) NMOS and PMOS characteristics.

 

 

A subset of the parameter histograms which can be produced by SPAYN are shown in Figure 2. The parameters in question are the threshold voltage adjust dose process input variable, the p-channel measured Beta parameter, the n-channel extracted PCLM model parameter, and the measured p-channel saturation region current for a bias of VGS = VDS = -5.0V with VBS = 0V. Figure 3 shows two scatter plots generated with SPAYN. The first plot is a graph of the gate oxidation pressure variable versus the extracted BSIM3 n-channel zero-biased threshold voltage parameter (VTH0). The correlation coefficient between these two quantities is 0.87. The second plot shows the threshold voltage adjust implant dose variable and the p-channel VTH0 parameter where the associated correlation coefficient is 0.77. It can be seen that for the experimental conditions in this example the NMOS VTH0 parameter was most sensitive to variations in gate oxide thickness whereas the PMOS VTH0 parameter was highly sensitive to the threshold voltage adjust implant.

 

Figure 2. Histograms for the vtadj_ds, pbeta,
N_PCLM, and P_Isat_m parameters.

 

 

 

Figure 3. Scatter plots showing gateox_p vs. VTH0_N and vtadj_ds vs. VTH0_P.

 

 

Principal component analysis (PCA) techniques were used to determine the critical input process variables and to generate a system of equations relating the extracted BSIM3 parameters to these process variables. In this example it was determined that the dominant process parameters were the poly CD, the gate oxidation pressure, and the threshold voltage adjust implant dose input variables. These three parameters accounted for over 70% of the variance of all of the extracted correlated BSIM3 parameters. The system of equations, generated by SPAYN, relating the BSIM3 model parameters to these independent process variables is partially shown in Figure 4.

 

 

Figure 4 SPAYN screen showing the some of the equations
relating the BSIM3 model parameters to the process input
variables poly_cd, gateox_p, and vtadj_ds.

 

 

The three identified independent dominant process variables were used to create nine (2^3) so-called "process corner" model sets. Since the NMOS and PMOS parameters were analyzed together, each model parameter set consists of an NMOS and a PMOS model. The variabilities of the BSIM3 model parameters, and the correlations which exist between these parameters, are taken into account in the construction of these corner models. In this example, each of the process variables was set to either its +3sigma or -3sigma values in order to create the required corner models. Worst-case model parameter sets can be identified from these process corner models for any given circuit application. Figure 5 shows the results of using the process corner models to investigate the effects of process variations on a simple CMOS inverter. The characteristics that are plotted are the voltage transfer characteristic and the supply current characteristic. The worst-case or best-case simulations for the trigger voltage are predicted by corner model set No. 5 and corner model set No. 4 resulting in trigger voltages of approximately 2.0V and 2.4V respectively. The worst-case or best-case simulations for the maximum supply current (trigger current) are predicted by corner model set No. 1 and corner No. 7. The resultant maximum and minimum supply currents are approximately 1.4mA and 0.65mA respectively. The circuit simulations were run directly from within SPAYN.

 

Figure 5. SmartSpice plots showing the CMOS inverter simulation
results where the derived process corner models are utilized.

 

 

Conclusions

An example demonstrating the results of the integration of process simulation, device simulation, parameter extraction, statistical parameter analysis, worst-case model generation, and circuit simulation was presented in this article. Using such a framework, invaluable

information regarding the relationships between SPICE model parameters and some core process variabilities can be determined. Assessments of circuit performance variability, sensitivity, and parametric yield for a process under development can be obtained.

 

References

[1] Simulation Standard, Vol. 6, No. 3, March 1995