Macromodeling of Operational Amplifier Circuit Performance using SPAYN

 

Introduction

SPAYN allows the statistical character of a semiconductor manufacturing process to be modeled at the SPICE model parameter level. When used in conjunction with a circuit simulator SPAYN allows the statistical variation of circuit characteristics to be accurately determined. Macromodels relating circuit performance variations to variation in the independent process-related device model parameters can be constructed.

In this article SPAYN is used with the SmartSpice circuit simulator to statistically evaluate some of the important AC and transient characteristics of an operational amplifier circuit. Regression macromodels are constructed for the unit gain frequency, phase margin, open loop gain and slew rate of a two-stage CMOS operational amplifier in terms of independent device model parameters.

 

Process Variations at the SPICE Model Parameter Level

Statistical modeling of the effects of process variations on circuit performances requires that representations of these variations must firstly be measured. The process variations in this example are represented by a database of SPICE Berkeley level 3 MOSFET model parameters which were obtained from over 350 wafer sites distributed over many different wafers for a CMOS process. The parameters which were logged during this experiment were the TOX, U0, LD, WD, RD, RS THETA, KAPPA, NSUB, ETA, GAMMA, NFS, VMAX and VT0 parameters for both NMOS and PMOS devices. The XJ, DELTA, PHI, and NSUB parameters were assigned constant process-dependent values for both device polarities.

A principal component analysis (PCA) with an 80% variance retained criterion was performed using SPAYN in order to identify the main sources of variation. Four principal components were found to account for 81.4% of the overall parameter variation. An inspection of th parameter groups obtained from the PCA indicated that these four components were related to variations in gate oxide thickness, polysilicon CD, threshold voltage adjust dose, and bird's beak respectively. The essentially independent dominant parameters associated with each group were VT0 (NMOS), LD(NMOS) U0(PMOS), and WD (NMOS) respectively.

A set of equations was produced using SPAYN in which the other non-dominant measure parameters were expressed in therms of a multilinear regression on these four dominant parameters. By varying the four dominant parameters randomly according to their distributions, and using the regression equations to calculate values for all the other parameters, SPAYN was used to generate a large set of properly correlated models for use in statistical Monte Carlo analyses. Examples of such equations were shown in a previous Simulation Standard article[1].

 

Operational Amplifier Circuit

Figure 1 shows a circuit diagram for the two stage CMOS operational amplifier was designed for power supplies of VDD=5V, VSS=-5V. The transistors M3, M4, M7 and M8 are PMOS devices, while all others are NMOS devices. Using a load capacitance (Cload) of 10pF, the SmartSpice optimizer was used to optimize device (W/L) dimensions so that the performance targets of:

 

Open loop gain (Ao) = 75db
Unity Gain Frequency (Fo) = 1MHz
Phase Margin = 60db
Slew Rate = 6 volts per microsecond

 

were met using the nominal set of device model parameters provided by SPAYN. The compensation capacitor Cc was chosen to be equal to the load capacitance in this example.

 

Figure 1. Two-stage CMOS operational amplifier.

 

 

 

Operational Amplifier Circuit Performance Extraction

The operational amplifier circuit performances of interest were Fo, the phase margin at unity gain, the open loop DC gain, Ao, and the rising slew rate (SR).

The following SmartSpice .MEASURE statements were used to extract values for the output Ao, Fo, and Phase Margin from the results of an AC simulation.

.AC DEC 10 1 10MEG
.MEASURE AC A0 point mag(v(out)) ARGO=1Hz
.MEASURE AC F0 cross mag(v(vout)) VAL=1
.MEASURE AC UnityGainPhase point phase(v(vout)) ARGO=F0
.MEASURE AC PhaseMargin EXPR VAL='UnityGainPhase + 180'

The first line specifies an AC simulation fro 1 Hz to 10MHz, with 10 steps per decade. The first .MEASURE statement calculates the magnitude of the output voltage relative to the unit input voltage at the point where the frequency was 1Hz. This gives the open loop gain (Ao). The second .MEASURE statement determines the value of the frequency where the output voltage magnitude curve crosses unity gain (Fo). The next .MEASURE statement calculates the phase at the unity gain frequency Fo. The final .MEASURE statement us an expression which calculates the phase margin as the difference between the phase at unity gain frequency and -180 degrees.

The operational amplifier was placed in a unity gain configuration with a large step applied to the positive input. A transient analysis was then run in order to obtain the rising slew rate. The following control statements were used:

 

VIN VA 0 pulse ( -5 5 1n 1n 3 u 1 )
.MEASURE TRAN Tom2 cross v(vout) val=-2
.MEASURE TRAN Top2 cross v(vout) val=2
.MEASURE TRAN SR EXPR val='4/(Top2 - Tom)/1e6'

 

The first line specifies a +/-5 volt pulse waveform applied to the input. The first .MEASURE statement (Tom2) calculates the time when the output voltage crosses -2 volts. The second .MEASURE statement (Top2), calculates the time at which the output voltage waveform crosses +2 volts. The slew rat (SR) is measured using a expression which calculates the ratio of the output voltage change to the time it occurred in (scaled to volts per microsecond).

Figure 2 shows the AC simulation wavforms for the circuit, obtained using the nominal set of models.

 

Figure 2. AC simulation waveforms for opamp of Figure 1.

 

 

Operational Amplifier Performance Distributions

A 500-point Monte Carlo simulation was performed for both the AC and transient cases in order to determine the statistical variations in the performance of the operational amplifier. In both cases, SPAYN produced a set of control statements for SmartSpice in which the four dominant parameters VT0 (NMOS), LD (NMOS), U0 (PMOS) and WD (NMOS) were varied randomly according to their fitted Gaussian distributions. The set of equations necessary to determine the values of the other device model parameters was also reproduced using SmartSpice control statements. At the end of the Monte Carlo simulations an output file was saved using SmartSpice and imported into SPAYN, allowing a statistical analysis of the results.

 

Figure 3 and 4 show the distributions of the unity gain frequency Fo (gamma distribution) and the slew rate (log normal distribution). It was also found that the open loop gain and the phase margin had gaussian distributions.

 

Figure 3. Unity gain frequency (Fo) distribution for CMOS opamp.

 

Figure 4. Slew rate distribution for CMOS opamp.

 

Figure 5 shows a strong relationship between the phase margin and the gate oxide thickness factor (i.e. NMOS VT0). The phase margin was also strongly related to the threshold voltage adjust factor (i.e. PMOS U0). Significant correlations were also found between the slew rate and the gate oxide thickness factor, and between the open-loop gain and the channel length reduction factor (i.e. NMOS LD). Closer inspection of the operational amplifier circuit implementation will show that such correlations are not unexpected[2]. These correlations suggest that good regression models can be obtained by relating the operational amplifier output performance variations to the independent dominant model parameter variations.

 

Figure 5. Relationship between phase margin and parameter VT0 (NMOS).

 

Macromodel Construction

The SPAYN Multi-Linear Regression feature was used to construct macromodels relating the operational amplifier performances to the dominant process-related SPICE model parameter variations. SUch macromodels are commonly used in circuit yield prediction and optimization methodologies [3,4,5].

In this example the macromodel multilinear regression equations are:

 

PhaseM = 42.39 + 6.25*VT0_N + 2.15E+05*WD_N + 0.05881*U0_P - 297.9 *LD_N
Fo = 3.7 - 3.129*VT0_N + 5.69E+04*WD_N - 0.001059*U0_P - 67.53*LD_N
Ao = 61.2 - 14.06*VT0_N - 4.118E+06*WD_N + 0.1052*U0_P + 4887*LD_N
SlewR = 30.13 - 30.24*VT0_N + 1.695E+05*WD_N - 0.005603*U0_P - 201.2*LD_N

 

Future versions of SPAYN will allow higher order and interactive terms to be used in the construction of such macromodel equations.

SPAYN also produced statistics which validated the goodness-of-fit of the models. Figure 6 shows a plot of the phase margin values estimated using the macromodel, versus the actual values obtained from the Monte Carlo analysis.

 

Figure 6. Simulated values (y-axis) versus estimated
macromodel values (x-axis) of phase margin.

 

 

Conclusion

This article has shown that the statistical variation in circuit performance characteristics can be predicted using a SPAYN-driven correlated Monte Carlo analysis. These variations must be taken into account by circuit designers at the circuit design stage in order that parametric yield be maximized. Accurate regression models, relating circuit performance variations to the independent process-related model parameter variations which cause them, can be constructed using SPAYN for use in yield prediction and optimization methodologies.

 

 

References

  1. The Simulation Standard, Vol. 6, No 1, January 1995.
  2. "Analog MOS Integrated Circuits For Signal Processing", Roubik Gregorian and Gabor C. Temes, published by John Wiley and Sons 1986.
  3. "Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI", Tat-Swan Yu, Sung Mop Kang, Ibrahim N. Hajj, Timothy N. Trick, IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No 6, November 1987.
  4. "Rapid Yield Estimation as a Computer Aid for Analog Circuit Design", Tamal Mukherjee, L. Richard Carley, IEEE Journal of Solid State Circuits, Vol. 26 No. 3 March 1991.
  5. "Parametric Yield Optimization for MOS Circuit Blocks:, Dale E. Hocevar, Paul F. Cox Ping Yang, IEEE Transactions on computer-Aided Design, Vol. 7, No. 6, June 1988.