Complete Simulation of SOI MOSFETs Using Nonisothermal Energy Balance

 

Introduction

The continuing trend for high speed circuits has resulted in a marked increase in the application of Silicon-On-Insulator (SOI) MOSFETs. However SOI MOSFETs offer a much more difficult simulation problem due to the presence of significant floating body effects, carrier heating and non-localized transport phenomena. The latest release of Silvaco's 2D semiconductor device simulator ATLAS now accounts for all non-localized and lattice heating effects. This article describes the results of ATLAS simulations which illustrate some common effects present in short channel SOI MOSFETs.

 

Effects of Lattice Heating on Device Characteristics

SOI transistors are expected to exhibit significant heating due to the low thermal conductivity of the insulating substrate. ATLAS has been used to obtain a set of typical ID-VD characteristics for a 0.8µm gate length SOI transistor with a film thickness of 0.16µm. As shown in Figure 1 when a gate voltage of 5V is applied a negative differential output resistance is obtained. As the drive current is increased the silicon lattice temperature increases and significantly degrades the carrier mobility so that, despite increasing the drain voltage, the drive current actually decreases.

Figure 1. Simulated SOI MOSFET characteristics where nonisothermal
energy balance properly predicts a negative differential resistance for VG=5V
due to reduced carrier mobilities at elevated lattice temperatures.

Lattice heating may also affect the breakdown characteristics. It has been observed that impact ionization rates are reduced at elevated lattice temperatures. Figure 2 shows the results of ATLAS simulations, both including (nonisothermal energy balance NEB) and excluding (energy balance EB) lattice heating, for identical bulk and SOI transistors. First, the significant lattice heating in SOI transistors has correctly affected their breakdown response, particularly in the deep breakdown regime. In the bulk transistor, however, lattice heating effects are negligible and the breakdown characteristics with and without lattice heating are identical. Secondly, ATLAS shows clearly that, due to the floating potential of the silicon layer turning on the lateral npn parasitic bipolar transistor, SOI transistors exhibit significantly lower breakdown voltages compared to bulk transistors.

 

Figure 2. Simulated breakdown shows that SOI transistors display lower
breakdown voltages compared to bulk devices due to a parasitic lateral bipolar
transistor but lower ionization coefficients due to increased lattice temperatures.

 

Floating Body Effects

The floating potential region present in SOI devices causes various floating body effects to occur. The most significant effect is the turning ON of the lateral bipolar transistor at low drain bias. ATLAS can be used to study the combination of bipolar/MOSFET operation by studying the effect of drain bias on the ID-VG characteristics. For low drain bias typical subthreshold characteristics are obtained as shown in Figure 3. As the drain bias is raised, for a gate voltage of 1V, the positive charge generated by impact ionization at the drain causes the potential of the floating body to increase. As a result, electrons are injected across the source junction and add to the existing channel current. Therefore, for the gate to turn the transistor OFF, a more negative gate voltage is required. If the drain voltage is further increased, the lateral bipolar transistor is fully turned ON and its collector current becomes the dominant component of the total current. At this drain voltage, the gate can no longer turn the transistor OFF as shown in Figure 3. This drain voltage is referred to as the holding voltage and it defines the maximum power supply voltage of SOI transistors.

 

Figure 3. Simulation of the dual bipolar/MOSFET action in SOI
transistors caused by the floating body region and the loss
of gate voltage control at high drain bias.