An Investigation of the Suitability of PCA Results Obtained from Selected Wafer Lots to Characterize Future Wafer Lots

Introduction

Principal Component Analysis (PCA) methodologies, or related techniques, are often used to analyze statistical model parameter data in order to enable the generation of model parameter sets for use in worst-case or statistical circuit design approaches [1,2] . The PCA is used to identify the core subset of independent or dominant model parameters. The results of the PCA are also used to aid in the construction of a system of equations relating the remaining non-dominant SPICE parameters to this uncorrelated parameter subset. In this article the results of a SPAYN PCA analysis, of model parameters extracted from selected wafer lots, are applied to measurements taken from a subsequent wafer lot. The object of this work was to investigate the accuracy of such an approach. The process-dependent dominant parameter subset may consist of SPICE-like parameters or electrical test parameters which were included in the initial PCA.

A PCA of complete SPICE model parameter sets sampled from selected wafer die will help the user to determine (a) the core set of process-dependent uncorrelated parameters, and (b) the equally process-dependent system of equations mentioned earlier. Ideally, in the case of a nominally stable process, it will only be necessary to measure the dominant parameter subset on future wafers. Complete model parameter sets can be constructed using the previously derived system of equations. In this way large databases of complete correlated SPICE model parameter sets can be generated very quickly and efficiently. The results can immediately be made available to parameter extraction or circuit design engineers. The time penalties associated with extracting statistically significant SPICE model parameter sets using conventional parameter extraction techniques are often considered prohibitive. Thus, the possibility of generating such important databases by routinely extracting a few independent dominant parameters is a desirable option. These resultant statistical parametric databases are essential in the composition of realistic parameter sets for use in statistical circuit design methodologies such as process corner (skew), worst case, or Monte Carlo circuit design techniques.

 

Analysis of Sampled Wafer Lot Data

Complete SPICE level 3 NMOS and PMOS parameter sets were extracted from wafer die sampled from selected wafer lots. The parameter sets included extracted model parameters and device currents measured under selected biasing arrangements. In all there were 38 quantities logged for every die. SPAYN was used to perform a PCA analysis on the entire parameter set and it was found that 5 independent components accounted for approximately 82% of the variance of the original correlated parameter sets. By correlating the parameters to the derived components the 5 dominant parameters were identified. The dominant parameters were LD (PMOS), TOX, KAPPA (NMOS), UO (PMOS), and WD (NMOS). These parameters accounted for 20.5%, 19.1%, 16.0%, 13.3%, and 12.8% of the variability of the complete parameter set respectively. The SPAYN user has the flexibility of changing the identity of these important dominant parameters if more suitable choices are required for reasons of physical meaning or extraction difficulty. A system of equations was then constructed which predicted the non-dominant parameters in terms of the non-correlated dominant parameters which were isolated. For simplicity a set of linear equations with no interaction terms was selected. This system of equations is given below:

IDPLS	=	381*LDP - 6986*TOX + 3.60e-06*KAPPAN
			+ 9.53e-07*UOP - 43*WDN +0.000140

SATPLS	=	7260*LDP - 1.96e+05*TOX - 0.00019*KAPPAN
			+ 2.52e-05*UOP - 745*WDN +0.002764

IDNLS	=	228*LDP - 10837*TOX - 0.00041*KAPPAN
			+ 2.82e-07*UOP + 367*WDN +0.000769

SATNLS	=	3085*LDP - 3.01e+05*TOX - 0.00093*KAPPAN
			- 1.21e-05*UOP + 5501*WDN +0.014712

VT0N	=	2.57e+05*LDP + 4.21e+07*TOX + 0.0653*KAPPAN
			+ 0.00449*UOP - 3.80e+05*WDN -0.73467

GAMMAN	=	90018*LDP + 3.08e+07*TOX + 0.00434*KAPPAN
			+ 0.00155*UOP - 71147*WDN -0.29266

NFSN	=	-2.21e+17*LDP + 1.71e+18*TOX + 1.34e+11*KAPPAN
			+ 5.03e+09*UOP - 7.68e+17*WDN -7.75e+11

LDN	=	0.338*LDP + 21*TOX - 3.07e-07*KAPPAN
		- 1.26e-09*UOP + 0.296*WDN -1.29e-07

U0N	-	5.8e+07*LDP - 2.85e+09*TOX -
10.3*KAPPAN
			+ 1.20*UOP + 1.24e+08*WDN +314

DELTAN	=	-	1.94e+05*LDP - 3.26e+07*TOX - 
0.03387*KAPPAN
		- 0.000334*UOP + 63493*WDN +0.8388

ETAN	=		38917*LDP - 11696*TOX + 0.00917*KAPPAN
		- 0.000685*UOP + 49830*WDN +0.14474

XJN	=	1.10*LDP - 36*TOX + 2.45e-07*KAPPAN
			- 8.45e-09*UOP + 1.19*WDN +2.19e-06

THETAN	=	-	2624*LDP - 4.26e+06*TOX -
0.004362*KAPPAN
		+ 0.000125*UOP + 584*WDN +0.11185

VMAXN	=	-	1.78e+10*LDP -
6.02e+12*TOX + 1.76e+05*KAPPAN
		+	743*UOP + 2.81e+09*WDN +94277

VT0P	=		2.03e+05*LDP - 
1.65e+07*TOX + 0.03516*KAPPAN
			+ 0.00499*UOP - 2.75e+05*WDN -1.4703

GAMMAP	= 	-	78014*LDP + 2.52e+07*TOX - 0.00376*KAPPAN
			- 0.00134*UOP + 61655*WDN +0.25365

NFSP	=	1.52e+18*LDP - 4.36e+19*TOX + 1.13e+11*KAPPAN
			+ 9.89e+08*UOP - 3.16e+17*WDN +8.54e+11

WDP	= 		-0.141*LDP + 3.89*TOX - 9.43e-09*KAPPAN
			- 1.58e-09*UOP + 0.906*WDN +2.58e-07

DELTAP	=	1.63e+05*LDP - 1.32e+07*TOX + 0.01333*KAPPAN
			+ 0.000887*UOP - 4.57e+05*WDN +0.48726

ETAP	=	50196*LDP - 3.82e+06*TOX + 0.00278*KAPPAN
			+ 0.000351*UOP - 42388*WDN +0.051086

XJP	=		0.603*LDP - 13.6*TOX + 9.21e-09*KAPPAN
			- 1.54e-10*UOP + 0.092*WDN +3.43e-07

THETAP	=	26940*LDP - 7.82e+06*TOX + 0.00139*KAPPAN
	  	+ 0.000828*UOP - 4033*WDN +0.14277

VMAXP	= -	1.52e+12*LDP - 
1.58e+13*TOX - 2.01e+05*KAPPAN
 	  	+ 3404*UOP + 1.77e+11*WDN +87466

KAPPAP	= 	-	1.66e+08*LDP - 1.27e+09*TOX - 22.4*KAPPAN
	 	+ 0.185*UOP + 5.01e+06*WDN +15.2

RSN	=	5.06e+06*LDP + 1.15e+09*TOX + 20.4*KAPPAN
 		- 0.157*UOP + 4.54e+06*WDN +23.0

RDN	=	5.06e+06*LDP + 1.15e+09*TOX + 20.4*KAPPAN
		- 0.157*UOP + 4.54e+06*WDN +23.0

RSP	= 	-	1.59e+07*LDP + 1.25e+09*TOX - 3.36*KAPPAN
	  	- 0.419*UOP + 2.93e+07*WDN +89.3

RDP	= 	-	1.59e+07*LDP + 1.25e+09*TOX - 3.36*KAPPAN
	 	- 0.419*UOP + 2.93e+07*WDN +89.3.

 

The quantity IDNLS was a linear region current measured from a 20/1mm NMOS device biased at VGS = 5V, VDS = 0.1V, and VBS = 0V. IDPLS was the corresponding PMOS measurement. SATNLS was a saturation region current measured from the NMOS device biased at VGS = VDS = 5V and VBS = 0V. SATPLS was the corresponding PMOS measurement.

 

Application of PCA Equations to a New Wafer Lot

The exact same parameter test and extraction procedures were applied to a completely different wafer lot (Lot_X) from the same CMOS process. Approximately 100 qualified parameter sets were extracted from this lot. The system of equations given above, in addition to actual measured values for the dominant parameters LDP, TOX, KAPPAN, UOP, and WDN were used to generate values for all of the other remaining parameters. These could then be compared with the real extracted values for all of these parameters. In this way it was possible to access the accuracy of using the PCA-based results obtained from the original sampled wafer lots to predict parameter sets on Lot_X .

Firstly, it was decided to examine the correlations between the dominant parameters extracted from Lot_X. The correlation matrix is shown in Figure 1 and it can be seen that, as expected, there were no significant correlations between these parameters.

 

Figure 1. The correlation matrix for the dominant parameter subset in Lot_X.

 

Next it was decided to compare some predicted parameter values for Lot_X to their measured counterparts. Figure 2 shows a histogram of the measured PMOS linear region current. Figure 3 shows the predicted histogram for this current where the system of equations derived from the previous wafer lots was used. In all cases the predicted parameter names have the letter "X" as a suffix. Figure 4 shows a scatter plot showing both of these parameters together. There is excellent agreement between both quantities. Figure 5 shows a scatter plot of the predicted and measured NMOS linear region currents. A scatter plot of predicted and extracted NMOS body-effect parameters is shown in Figure 6 while the equivalent PMOS parameter pair is displayed in Figure 7. Table 1 gives some more detailed information about these scatter plots as calculated by SPAYN. The mean and maximum errors in Table 1 refer to the straight line fit between the predicted parameter and measured parameter as shown in the scatter plots. It seems that the newly measured dominant parameter data, and the system of linear equations which were derived for previously gathered data, were sufficient to give fairly accurate predictions of most of the non-dominant parameters in this new wafer lot (Lot_X). The parameter means, variances and correlations have been reproduced very successfully.

 

Figure 2. Histogram of the measured PMOS linear
region current (IDPLS) for Lot_X.

 

Figure 3. Histogram of the predicted PMOS linear
region current (IDPLSX) for Lot_X.

 

Figure 4. A scatter plot showing the predicted and measured
PMOS linear region current measurements for Lot_X.

 

Figure 5. Scatter plot showing predicted and measured
NMOS linear region current measurements for Lot_X.

 

Figure 6. A scatter plot showing the predicted and measured NMOS
body-effect parameters (GAMMAN) for Lot_X.

 

Figure 7. A scatter plot showing the predicted and measured
PMOS body-effect parameters (GAMMAP) for Lot_X.

 

Figure 8. A scatter plot showing predicted and measured
NMOS static-feedback parameters (ETAN) for Lot_X.

 

 

However, it is important to note that parameters which had small variances explained by the original PCA analysis will probably not be adequately predicted in the manner described here. For example, only 49% of the variance of the NMOS ETA parameter (ETAN) was explained by the five derived principal components in the original PCA. Figure 8 is a scatter plot of predicted ETAN versus extracted ETAN data for Lot_X. The relevant data for this parameter pair is also included in Table 1. It is obvious that this parameter was not adequately recreated in this experiment. The variability of this parameter is grossly under-estimated and the correlations between this parameter and other parameters in Lot_X, if any such correlations exist, would not be accurately predicted by the simulated data. It is however possible that ETAN was not highly correlated to many other parameters in the original analysis because the variance of ETAN was not covered very well in the original PCA. In this case the potential correlation related inaccuracies incurred in this experiment would not be significant.

  IDPLS IDNLS GAMMAN GAMMAP ETAN
Predicted Mean 1.869E-4 5.756E-4 0.5839 0.4984 3.172E-2
Actual Mean 1.865E-4 5.651E-4 0.5835 0.4987 3.195E-2
Predicted Standard Deviation 7.619E-6 2.488E-5 4.938E-3 3.210E-3 1.270E-3
Actual Standard Deviation 6.928E-6 2.429E-5 3.756E-3 3.932E-3 2.517E-3
Mean Error 0.4% 2.0% 0.3% 0.3% 7.7%
Maximum Error 1.1% 4.9% 1.5% 1.1% 18.8%
Correlation Coefficient 0.99 0.89 0.92 0.89 0.13
R-squared Value 0.99 0.79 0.85 0.80 0.02

Table 1. Comparison information for selected parameters for Lot_X.

 

 

Conclusions

This article described how a PCA of parametric data sampled from wafers from a nominally stable IC manufacturing process can be used to (a) determine the core set of independent process-related parameters, (b) construct a set of equations relating the remaining correlated parameters to these dominant parameters, and (c) use this information to predict the correlated parameters from dominant parameter measurements on future wafers. An assessment of this methodology was performed using an example.

 

Acknowledgement

Silvaco would like to thank Barry Mason and Paul Stribley of GEC Plessey Semiconductors, Roborough, England, and Rory Clancy and Kevin McCarthy of the National Microelectronics Research Centre, Cork, Ireland, for their valuable contributions. The data used in this article was supplied by GEC Plessey Semiconductors, from their 6" wafer fabrication plant in Roborough, U.K., and came from the production 1.0mm CMOS analog process.

References

[1] "Accurate Worst-Case Model Generation with SPAYN"
Simulation Standard, Vol. 5, No. 2, 
	October 1994.

[2] J.A. Power, B. Donellan, A. Mathewson, and W.A. Land
"Relating Statistical MOSFET Model 	Parameter Variabilities 
to IC Manufacturing Process Fluctuations Enabling Realistic 
	Worst Case Design." 
IEEE Trans. on Semiconductor Manufacturing, Vol 7, No. 3, Aug, 1994.