Quasi-3D Thyristor Latch-Up Simulations

Introduction

Simulations of thyristor latch up have traditionally been a difficult, sometimes impossible, task. The switching of the device is an extremely discontinuous process with timescales that can be < 1ns. This is numerically difficult to handle, especially for steady-state simulations. Simplifying the device to a diode, applying a forward voltage and then introducing the p-base doping was one of the many approaches used in recent years. These techniques were either inconvenient, unphysical or numerically problematic. Simulations at blocking biases near the latch-up point were often impossible. In addition the injection of carriers required for turn on was a problem. Including a gate contact to do this is often not convenient since actual devices have huge lateral dimensions (several mm) which would require a vast number of nodes.

With the recently implemented curve-tracer algorithm and the LUMINOUS module, ATLAS is able to overcome such problems. It can address the objectives of a thyristor device engineer. In the first part of this article, the optimization of the blocking capability, a typical design task, is demonstrated. Behavioral models of lifetime-dependent properties are derived in the second part. Finally a transient example of a light triggered thyristor is described. All simulations take advantage of the cylindrical symmetry of the devices They are done in 2D using cylindrical coordinates. The terminal currents are in Amperes instead of current per micron of width.

 

1/ Thyristor Blocking Voltage Optimization

The voltage rating of a vertical thyristor for a given thickness is limited by two effects: a) impact ionization for high doped n-bases, b) punch through for low doped n-bases as the space charge region approaches the anode junction. To achieve the maximum blocking voltage, an optimum trade-off of these effects has to be found. The thyristor cell used here (Figure 1) is not a simple 4 layer structure. There is a direct connection of the p base region to the cathode metalization (short). A certain amount of leakage current is drained with this short to enhance properties such as blocking capability and forward dV/dt rating. In order to study and control the short current separately, the cathode electrode is divided into a pure cathode contact and a short contact.

 

Figure 1. Cross section of thyristor showing
position of the short contact.

Driving the voltage over the latch-up point is hampered by the abrupt change of the device impedance from very high values to virtually zero. The curve-tracer available in the current ATLAS release dynamically applies a load resistor into the current path, and automatically controls the steping of the external voltage. This "adaptive load line control" [1] allows ATLAS to trace out for arbitrary shaped I-V curves with multiple of turning points. Figure 2 shows a typical I-V curve for a n-base doping of 1.7x1013. It can be seen that the cathode contact picks up the majority of the current once the latch-up start. In blocking state only the short contact carries the current.

 

Figure 2. Typical thyristor breakdown
and snapback curve.

 

The latch-up starts at a current level, where the leakage current can no longer be drained completely through the short. The voltage drop under the cathode emitter rises above a limit Ucrit were the emitter gets forward biased. The critical current Icrit can easily be derived analytically. For cylindrical devices one gets:

 

 

where: Rs: sheet resistance of the p-base

r0: radius of the short (12.5 mm)
r1: radius of the cell (800 mm)
Rcont: contact resistance of the short
 

With DeckBuild's EXTRACT Rs can be derived directly and gives: 665 Ω/. With a simple 1D-simulation one gets 10.3 Ωfor Rcont. Assuming Ucrit to be 0.5V, Icrit equals to 1.25 mA. Using this data the simulation was carried out as follows: The voltage was ramped up with the curve tracer until the anode current exceeds 0.4 mA. At this level the voltage is already equal to breakdown, but the current is well below the latch limit. The following quantities were extracted:

a) the maximum Voltage (Vmax),
b) the "herlett zone"-thickness (herlett). This is the distance between space charge region
and anode-side junction,
c) the voltage drop under the cathode emitter (Von),
d) the leakage current Ileak

The ramp is continued further above the latch-up point and Icrit is extracted.

The Automation Tools of Virtual Wafer Fab (VWF) were utilized to make an experiment with the base doping as a variable stepped from 1x1013cm-3 to 1.7x1013cm-3 in steps of 0.5x1012cm-3. The required CPU-time per run is 15min on a SPARC20. This gives less then 2 hours for the whole experiment on a dual processor machine. Figure 3 shows the model of Vmax The shape is in excellent agreement with experience.

 

Figure 3. Dependence of Vmax on n-base doping
extracted using VWF response surface modeling.

 

 

From VWF's analytical model the optimum base doping is 1.4x1013cm-3. The maximum voltage rating for this design would be 6400V (assuming the spread of the doping concentration to be &plusmn; 5%). As expected the space charge region is linearly dependent on the base doping for high doped bases, but cannot touch the anode junction (Figure 4). For the given lifetime (15 µs for electrons 5 µs for holes) the limit seemed to be about 5 µm. Within the optimum base-doping range, herlett is 50 - 100 µm. The average Icrit of all simulations was 1.21 mA, with a standard deviation of only 1.7%. Scaling Von with Icrit/Ileak to get the voltage drop at Icrit gives an average for all simulations of 0.46V (&plusmn; 0.8%). This is in good agreement with the assumed value of 0.5V that had been used in the equation for Icrit.

 

Figure 4. Dependence of 'herlett'zone
threshold on n-base doping

 

 

2/ Lifetime dependence of onstate and blocking

Minority carrier lifetime tailoring is one of the most important objectives for power device engineering. Irradiation and diffusion technologies with noble metals are used to reach an optimum trade-off of several correlated device properties. To study the lifetime dependence of on-state losses and blocking voltage capability, the optimized design found in section 1 (base doping = 1.35x1013cm-3) was used. The electron lifetime (te) was stepped from 10 ms to 50 ms, the hole lifetime (th) being varied so it is kept at 33% of te. The lifetime was assumed to be uniform except for dependence on the doping concentration. To extract Vmax the same procedure as in Section 1 was used. In order to save CPU time, the simulation was stopped below latch-up, and the on-state was simulated by using the short electrode as a gate. The required CPU-time for a run was 6-7 min per simulation. It took less than 1 hour for the whole experiment.

The anode and short contacts were simultaneously driven to 4V. Then the short was ramped down to 0V. From this high onstate condition the anode was ramped down until the device starts to block again. At this point several important device parameters were extracted. The minimum current to hold the onstate (Ihold), the minimum voltage (Vth), and the voltage drop at 1A (V@1A). This current corresponds to a current density of 78 A/cm. It can be seen that there is a strong lifetime dependence for te < 20 µs for all onstate properties (Figure 5), whereas Vmax depends more or less linearly with te (Figure 6). Ihold and Vth seem to be unrealisticly high. This might be due to the fact that on a real device the fraction of the total emitter area being in the high injection condition will shrink with decreasing current. This cannot be modeled with a single cell. Plotting Vmax against V@1A gives a technology curve which can be used to tune the tradeoff with lifetime techniques.

 

Figure 5. te dependence of on-state characteristics.

 

Figure 6. Vmax dependence on te shows the possible
gains in power rating through lifetime tailoring.

 

 

3/ Light triggered thyristor

Due to the very high voltage ratings of power thyristors, the control circuit and the device itself are sometimes decoupled by light. A light triggered thyristor could be be the most elegant device for many applications. The example shown in Figure 7 has an amplifying gate. This is a small thyristor which feeds its whole current into the gate of the main thyristor. To make the amplifying gate thyristor more sensitive to latch, the emitter is put in a recessed region. This enhances the resistance of the path for the current flowing from the irradiated region to the short and also the voltage drop under the emitter. Using steady-state simulation it was shown that for turn-on a light power of 1.8mW corresponding to 4.57mA photo current was required. If the amplifying gate were disabled and its metalization was removed 16.5 mW (13.8mA) is required. This gives an amplification factor of 9.2. Shining the light from this side directly into the blocking junction under the cathode requires 3.0 mW of light power (3.5 mA). This shows clearly that a lot less current is required for turn on when a point-like current source is put in the middle of the cathode. In the case of homogeneously distributed current, the given formula would predict 4.0 mA. As expected, this is inbetween the two cases with point-like current sources. A transient simulation shows how the current starts to flow through the short after an instantaneous turn on of the light (Figure. 8). After about 4 ms the short current has reaches 1 mA and the cathode emitter starts to inject. After this delay, it takes only 0.58 µs to latch the device. The anode voltage dropped from 90% to 10% of the supply voltage. The total CPU time required was less than 20 min.

 

Figure 7. Section of light controlled thyristor showing
the position of the amplifying gate contact.

 

Figure 8. Thyristor response to a transient light
pulse. Latch up occurs at 0.58 ms

 

 

This example shows the usefulness of ATLAS for performing practical tasks in the design of a light triggered thyristor and the use of Luminous to generate carriers in the device. This allows users to perform simulations without the need to use huge gate structures (for instance this could be done in 1D) making the task much simpler and faster.

 

Summary

These results show that common problems of performing simulations of thyristors can be easily solved with the ATLAS device simulator. With the curve tracer, ATLAS proves to be a reliable and robust tool to handle discontinuous steady-state and transient latchup simulations. The latchup current levels are in excellent agreement with theory. Steady-state gated turn-on has been demonstrated. Luminous allows simulation of light triggered devices and to generate turn on currents where a gate structure is not available. When combined with the automation tools of the VWF, a powerful TCAD tool is available to derive important design trade-off curves.

 

References

[1] Goosens et. al., IEEE Trans. Computer Aided Design of Integrated Circuits and Systems, 13, No.3, 1994.