Automatic Layout to SPICE 3D Interconnect Modeling

For modern technologies, interconnects have become at least as important as the active semiconductor devices in terms of determining overall chip performance. To predict the performance of a technology it is not enough to rely on conventional device simulation of transistors. Accurate simulation of interconnect structures is also required. A new 3D interconnect capacitance and conductance simulator is now available as part of the ATLAS device simulation program. This module, called Interconnect3D, provides a direct path from layout to structure creation to parasitic extraction to SPICE sub-circuit output.

 

Models

Interconnect3D performs a full self-consistent solution of the Laplace equation for 3D structures. This equation is used to describe the electrical potential in both non-ideal conductors and insulators.

The technique used is the energy conservation method. This method is both accurate and physically based and has many advantages in accuracy over the geometrical approach used in parasitic extraction from IC layout environments. Geometrical approaches do not generally account for shielding and proximity effects correctly. These effects are becoming very important as more metal layers are added.

 

Interfaces

Interconnect3D has a simple interface to MaskViews to allow calculation of interconnect parasitics from layout information. It also has an interface to process simulation to provide realistic topography for the interconnect structure. The easy to use interface to IC layout means Interconnect3D can be used by engineers who are not typical users of device simulation. One important issue in the IC layout interface is connectivity of the metal tracks as they pass between layers in the layout. Interconnect3D contains a sophisticated algorithm to work out the connectivity of the tracks. It is able to reduce metal regions in multi layer structures to the minimum number of unconnected interconnects

before doing the capacitance calculation. As more and more interconnect layers are used, the topography of the interconnects becomes more complex. For accurate simulations of interconnect capacitances it is obviously necessary to have a good description of the topography of the interconnect. Interconnect3D is interfaced to the Elite module of ATHENA which is able to produce accurate cross-sections of multi-level interconnects. It is also interfaced to SSuprem4 for simulation of the effect of oxidation on topography such as bird's beak shapes.

 

Results

Figures 1, 2 and 3 show the original layout, the mask level visualization and a structure created from layout. This structure is then analyzed to produce output in the form of SPICE subcircuit syntax. There is no artificial separation of the capacitance into overlap and fringing portions such as geometrical parasitic extraction programs do. However it is possible from two or more simulations to reconstruct these artificial partial capacitances for use in circuit simulation.

 

 

Figure 1. The layout used to create
the structure shown in Figure 3.

 

Figure 2. The layout editor includes a convenient tool for
visualizing the individual mask levels in 3D.

 

Figure 3. 3D structures for interconnect analysis
(such as this) can be easily created wit ATLAS.