The Silvaco Solution For Technology CAD

Several years ago Silvaco decided to become a "full spectrum" supplier of semiconductor technology CAD software. The associated technical strategy involved three primary thrusts:

  • assemble previously fragmented subareas of CAD into a single coherent discipline, "semiconductor technology CAD";
  • modernize the tools in each area to bring them into the modern era of interactive, workstation-based computing; and
  • integrate the unified, modernized capabilities within a user-oriented CAD system

These goals have all been achieved! The purpose of this article is to explain Silvaco's integrated solution for semiconductor technology CAD. The article does more than provide a clear overview of Silvaco's innovative products. It also demystifies a technical area that has previously been made to appear unnecessarily complicated.

 

Semiconductor Technology CAD

The scope of semiconductor technology CAD (S-TCAD) is the complete set of CAD activities associated with the development of semiconductor technologies. The core activities of S-TCAD are physically-based simulation of processes, devices and circuits. These simulation capabilities are supplemented by several types of data modeling tool. Device modeling and parameter extraction software is a specialized type of data modeling tool that provides specialized support for circuit simulation. Other data modeling tools apply to more general data, and implement either deterministic or statistical modeling approaches. Semiconductor technology CAD also includes "utilities" that make it more convenient to use combinations of simulators and modeling tools, and "design systems" that make it easier to perform large-scale simulation-based studies.

As shown in Figure 1 this definition of S-TCAD leads to a "generic" block diagram for S-TCAD environments. Virtually any S-TCAD product line can be mapped on to this block diagram. Of course, particular solutions and product lines will differ greatly with respect to which areas they implement, how data flows between areas, and how the user interacts with the system.

 

Figure 1: A generic block diagram for S-TCAD environments.

 

This generic block diagram contains the implicit assumptions that a division of microelectronics CAD into S-TCAD and circuit design CAD(so-called ECAD) is appropriate, and (ii) that any further division of S-TCAD into isolated sub-specialities is to be avoided. These issues will now be discussed.

 

Partitioning Microelectronics CAD

The division of microelectronics CAD into S-TCAD and ECAD reflects the way that industry partitions its product development activities. There is an excellent reason for this division. The requirements for optimizing a semiconductor technology to yield good circuit performance can usually be reduced to a "rules of thumb" based on electrical figures of merit(e.g. maximize drive currents, minimize capacitances, leakage currents and power dissipation, meet noise margin requirements, etc.). It is usually much more practical and efficient to incorporate these goals explicitly into the optimization of a semiconductor technology, rather than implicitly into simultaneous technology and circuit.

The partitioning does not imply that there are no connections between S-TCAD and ECAD. It means that the existing connections are not a source of significant inefficiency in the product development process. Overlap between S-TCAD and ECAD occurs very naturally at the level of circuit simulation. Viewed as part of technology design, the simulation of typical subcircuits verifies the appropriateness of process and device design. Viewed as part of circuit design, circuit simulation is used to establish circuit characteristics accurately, before proceeding to design activities that are performed at higher levels of abstraction.

 

Integrating Technology CAD

There are at least three reasons why the integration of S-TCAD capabilities within a single system is highly desirable. Three important features that can be incorporated into an integrated system are: the transparent management of data flow; the exploitation of subtask engineering task level automation.These will now be outlined in turn.

Data travels to and fro between process simulation, device simulation and circuit simulation. Data also flows from device measurements (or devices simulation), through device modeling and characterization, to circuit simulation; and between simulation tools and data modeling tools. Using tools in combination can be difficult when the user is responsible for data management. It is much more convenient when data transfer is handled transparently.

Subtasks, such as data visualization and griding, are associated with several different tools. . Integration allows the exploitation of this commonality, using utilities that perform the subtasks in a consistent way for all the simulators in a system. This makes it easier to learn to use several different tools.

Most users prefer to interact with a CAD system at an application-oriented level of abstraction. An integrated system can make this possible. Once the system has been set up properly (i.e.calibrated, and stocked with descriptions of layouts, process flows,and electrical tests) engineers who are not simulation specialists can easily perform simulated experiments. This is an excellent way of obtaining the benefits of simulation throughout an organization, and by leveraging on the knowledge of experts.

 

The Starting Point

When Silvaco started the implementation of an integrated system in 1989 the field of semiconductor technology CAD was fragmented. Different companies were active in the areas of process and device simulation, device modeling and characterization, and circuit simulation.

Silvaco's UTMOST product provided a strong base in the area of device modeling and characterization. In the other core areas Silvaco started from university codes such as SPICE from the University of California at Berkeley, and PISCES and SUPREM IV from Stanford University. All the other capabilities required by an integrated system had to be developed in-house.

 

The Development Path

The first step was the development of PISCES and SUPREM IV into cost-effective products. Innovative new capabilities were added, and a set of interactive tool integration utilities was implemented. Parallel efforts resulted in the development of the SmartSpice circuit simulator and the SPAYN tool for statistical analysis. A set of task integration tools was implemented, and the process and device simulation capabilities were rewritten as ATHENA and ATLAS. The final step was to ensure that all of the components work together seamlessly. This step has now been completed.

The products that from Silvaco's integrated solution for semiconductor technology CAD are shown in Figure 2. The system make it very convenient to perform studies that were previously not practical. For example, worst-case SPICE model parameters can be generated automatically from layout and process flow information. This is a true landmark in the development of semiconductor technology CAD!

 

Figure 2. The Silvaco solution for semiconductor CAD.

 

The Silvaco Solution

The individual components of the SIlvaco solution will be reviewed briefly. An example of the practical application of the system is provided in the next section.

 

Physically-Based Simulators

The physically-based simulators are: ATHENA, for process simulation; ATLAS, for device simulation; and SmartSpice, for circuit simulation. ATHENA and ATLAS are modular, second-generation process and device simulation products. They are described in more detail in other articles in this issue. SmartSpice is a modern, versatile, fast, accurate circuit simulator.

All three physically-based simulators can be used in conjunction with the C-Interpreter, which allows users to modify existing models and define and use their own models. This capability is very popular with industrial an academic research groups.


Device Modeling and Characterization

UTMOST is a general purpose device characterization and modeling tool. UTMOST enables the user to determine accurate circuit simulator model parameter sets for a wide range of device types using fitting, local optimization and/or global optimization techniques. UTMOST can perform the measurement, prober control, and parameter extraction task. All commonly used commercial device models, including the modern BSIM3 Version 2.0 MOSFT model, are supported, and user-defined or proprietary models can easily be included using dynamically linked libraries. Macro modeling is also supported. UTMOST can be operated in fully interactive, semi-automatic, automatic, or batch modes.

SPAYN is a statistical analysis software package targeted specially at the semiconductor industry. The main motivation behind the use of SPAYN is the determination of accurate worst-case or "process corner" model parameter sets. SPAYN interfaces with most commercially available circuit simulators, including Silvaco's SmartSpice, and allows direct feedback on the effects of statistical process fluctuations on specified circuit performances. SPAYN can also be used to determine the important relationships between electrical test parameters, SPICE model parameters, and circuit test information. When used in conjunction with the Silvaco system, SPAYN can be used to generate process corner models and determine their effects on circuit performances for a process under development.


Utilities

The tool integration utilities are DeckBuild, TonyPlot, DevEdit, MaskViews and Optimizer. DeckBuild provides an interactive run time environment. TonyPlot provides comprehensive capabilities for scientific visualization. DevEdit supports structure editing, mesh generation and user-controlled or adaptive refinement of meshes. MaskViews provides a layout interface and editor, and Optimizer provides sophisticated black-box optimization capabilities. Optimizer works across tools, which means, for example, that process parameters can be varied to optimize electrical targets.


Design System

Silvaco's design environment, the Virtual Wafer Fab (VWF), automates all of the activities associated with carrying out simulated experiments. It takes care of the otherwise time-consuming, tedious and error-prone tasks of specifying experimental design, generating and submitting the associated simulation runs in a networked computing environment, and managing the input and output data. The Virtual Wafer Fab also takes care of modeling the data that is generated, and performing additional calculations associated with design, and optimization. The latest version of the software also performs post-processing associated with yield analysis and failure analysis, suitable for manufacturing applications.

 

An Example

This example demonstrates how the integrated solution is used to predict the impact of process variations on worst-case SPICE model parameters. The study is for a standard twin-well CMOS process using LDD structures. The transistors have degenerately doped n polysilicon gates, a nominal gate length of 0.6 µm, and a nominal gate oxide thickness of 18 nm. The PMOS transistor is a buried channel device.

The first step is to define individual or "unit" simulations that form the building block of the study. The unit simulations for this study involve the use of ATHENA, ATLAS and UTMOST in combination. The input to ATHENA is defined by a region of masks layout that includes the devices to be simulated and a baseline process flow defined using ATHENA input syntax. The NMOS and PMOS devices are specified using cutlines on the mask layout.

The device simulation is defined by using standard device test form the VWF device test library. The characterization to be performed (BSIM3 parameter extraction in this study) is specified using modules form the characterization library. The linking of mask data, process flow date, standard device tests and characterization modules is performed interactively using th flow Editor. The associated procedures are described in detail in the Hints, Tips and Solutions column in this issue.

The second step is to design and run the simulated experiment. This involves running multiple unit simulations that correspond to variations of the baseline process flow and/or the nominal layout data. The simulated experiment is defined interactively in the Virtual Wafer Fab (see Figure 3). The unit simulations are then generated and run automatically in a networked computing environment, and the results are written automatically to a worksheet. Figure 4. shows a fragment of a typical worksheet.

 

 

Figure 3. The simulated experiment is defined interactively.

 

Figure 4, A fragment of a Virtual Wafer Fab worksheet.

 

The third step is statistical analysis of BSIM3 model parameters using SPAYN. Only a glimpse of this process will be given here. Figure 5 shows a portion of a parametric short-form statistical table. Figure 6. shows representative histogram plots and Figure 7 shows scatter plots of selected parameter pairs. A principal component analysis indicated that four independent components explained 81.5% of the variance of all the NMOS and PMOS parameter analyzed. A set of 16 (2) corner models was then generated. Worst-case model parameter sets for any circuit application can be selected from these corner models.

 

 

Figure 5. A portion of a parametric short-form statistical table.

 

Figure 6. A typical histogram plot produced as output by SPAYN.

 

Figure 7. A typical scatter plot produced as output by SPAYN.

 

Figure 8 shows the results of simulating the transfer characteristic of a simple CMOS inverter with all 16 process corner models. These simulators were performed by SmartSpice under the control of SPAYN. Worst-case models based on trigger current or small-signal gain are easily identified and the critical process variations can subsequently be traced. More details of the work are presented elsewhere [1].

 

Reference

[1] Worst-Case SPICE Model Generation For A Process in Development Using ATHENA, ATLAS, UTMOST,and SPAYN, VWF/SPAYN Application Note, Reference No. SP/94/002, Silvaco International, 1994.