Accurately Simulate Your Nonvolatile Memories

 

Dr. E.Lyumkis, Dr. B.Polsky, A.Shur, A.Strachan, Dr. A.Tcherniaev, and Dr. P.Blakey

 

Do you need to investigate, verify, and optimize designs for nonvolatile memories, such as EPROMs, EEPROM s, and Flash EEPROM s? Then you need a device simulator to account for a variety of physical effects such as band-to-band tunneling, Fowler-Nordheim tunneling, impact ionization, and floating gates! Self-consistent descriptions of these effects (not just postprocessing approximations) are required. Both steady-state and time-domain transient simulation capabilities are desirable. Time-domain capabilities provide self-consistent (rather than less accurate quasi-static) calculations of <->programming and erasing operations.

These capabilities are incorporated in the robust general purpose device simulators HFIELDS-2D and S-Pisces 2B. Charge boundary conditions, Fowler-Nordheim tunneling and band-to-band tunneling are all self-consistently simulated. In addition, a newly developed numerical algorithm that greatly reduces the mesh sensitivity of calculated gate current is used. This mesh sensitivity limits the accuracy and reliability of some other programs that seek to simulate nonvolatile memory devices.

HFIELDS-2D and S-Pisces 2B provide versatile, accurate, and robust steady-state and transient simulation of nonvolatile memory devices. In steady-state simulation, an arbitrary charge may be specified on the floating gate. By this means it provides threshold voltage versus charge and estimates of charging and discharging rates. In transient simulation, the charge associated with the hot electron and Fowler-Nordheim currents is applied to the floating gate at each time step. This allows complete transient simulation of programming and erasing.

The following EEPROM simulations were generated using S-Pisces 2B to illustrate the effect of varying the tunnel oxide thickness from 75 to 120. The device structure (Figure 1, front page) was generated by SSuprem4. The channel length is 0.7 microns and the gate oxide thickness is 200. Figure 2 (front page) shows the erase characteristics associated with different tunneling oxide thicknesses. Erase time is very dependent on oxide thickness because Fowler-Nordheim tunneling is very sensitive to electric field.

 

Figure 1. Initial structure for EEPROM
simulation generated by SSUPREM4.

 

Figure 2. EEPROM device simulation showing erase
characteristics associated with different
tunneling oxide thicknesses.

 

 

Figure 3 illustrates the importance of accounting for band-to-band tunneling during erasure. The substrate current behavior during erasure cannot be determined accurately without accounting for tunneling effects in the model. Figure 4 shows threshold voltage shift as a function of the charge on the floating gate. Figure 5 shows gate current dependence on the control voltage. Figure 6, transient programming characteristics for different drain voltages, clearly demonstrates the strong dependence of programming times on drain-source voltage.

 

Figure 3.

 

Figure 4.

 

Figure 5.

 

Figure 6.

 

HFIELDS-2D and S-PISCES 2B now both provide general, effective, and robust simulation capabilities for nonvolatile memory devices. These features are implemented in the Nonvolatile Memory Design Module (NVM), one of SILVACO's Industrial Applications Modules. This module is currently available.