Published Papers

FinFET

The full text for most of these papers may be found at the IEEE website at www.ieee.org.

A. Yesayan, N. Chevillon, F. Prégaldiny, C. Lallement,
"Compact physics-based model for ultrashort FinFETs",
2010 Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2010, pp. 75 - 80.

Seongjae Cho, Jung Hoon Lee, Shinichi O’uchi, Kazuhiko Endo, Meishoku Masahara, Byung-Gook Park,
"Design of SOI FinFET on 32 nm technology node for low standby power (LSTP) operation considering gate-induced drain leakage (GIDL)",
Solid-State Electronics, Vol. 54, Issue 10, October 2010, pp. 1060-1065.

M. Moreau, D. Munteanu, J.L. Autran,
"Simulation study of Short-Channel Effects and quantum confinement in double-gate FinFET devices with high-mobility materials",
Microelectronic Engineering, In Press, Corrected Proof, Available online 6 September 2010.

M.A. Pavanello, J.A. Martino, E. Simoen, C. Claeys,
"Cryogenic operation of FinFETs aiming at analog applications", Cryogenics, Vol. 49, Issue 11, November 2009, pp. 590-594.

M.A. Pavanello, J.A. Martino, E. Simoen, C. Claeys,
"Cryogenic operation of FinFETs aiming at analog applications Cryogenics",
In Press, Corrected Proof, Available online 3 January 2009.

P. Magnone, V. Subramanian, B. Parvais, A. Mercha, C. Pace, M. Dehan, S. Decoutere, G. Groeseneken, F. Crupi, S. Pierro,
"Gate Vol.tage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices",
Microelectronic Engineering, Vol. 85, Issue 8, August 2008, pp. 1728-1731.

A. Kranti, et.al.,
"Optimizing FinFET geometry and parasitics for RF applications",
IEEE International SOI Conference, 2008, pp.123-124, Oct. 2008.

Ismail Saad, Razali Ismail,
"Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method",
Microelectronics Journal, In Press, Corrected Proof, Available online 7 May 2008.

A. Kranti et al.,
"Comparative analysis of nanoscale MOS device architectures for RF applications",
Semiconductor Science and Technology, Vol. 22, No. 5, pp. 481-491, 2007.

A. Kranti et al.,
"Significance of gate underlap architecture in FinFETs for low–Vol.tage analog/rf applications",
211th Electrochemical Society Meeting (Chicago, USA), In Proc. ECS Transactions (SOI Device Technology), Vol. 6, No. 4, pp. 375-380, 2007.

A. Kranti et al.,
"Comparative analysis of nanoscale MOS device architectures for RF applications",
Semiconductor Science and Technology, Vol. 22, No. 5, pp. 481-491, 2007.

A. Kranti et al.,
"Device design considerations for nanoscale double and triple gate FinFETs",
In Proc. 2005 IEEE SOI Conference, Honolulu, Hawaii, USA, pp. 96-98, 2005.

Byung-Kil Choi, Kyoung-Rok Han, Young Min Kim, Young June Park, Jong-Ho Lee,
"Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs) Electron Devices"
IEEE Transactions on Vol. 54, Issue 3, March 2007 pp. 537 - 545.