SmartSpice BSIM3 v3  
UC Berkeley released the final version of the BSIM3v3 model in October, 1995. This model is now available in SmartSpice 1.4.0 in two different variants. The SmartSpice implementation is referred to as MOSFET model level 8. The original Berkeley model is also available within SmartSpice as MOSFET model level 81. Both models produce virtually identical results when commonly acceptable model param eter sets are used. However, these models are not identical since the SmartSpice implementation provides a number of additional parameters currently not supported in Berkeley Spice. This application note describes the SmartSpice BSIM3v3 implementation and the primary differences between SmartSpice level 8 and level 81 models.
SECTION 1

Parameter  Description  Units  Default 

COX  Gate oxide capacitance  F/m2  
ACM  Area calculation method  0  
GEO  Geometry model selector (for ACM = 3)  0  
METO  Fringing factor  m  0 
RD  Drain ohmic resistance  Ohm  0 
RS  Source ohmic resistance  Ohm  0 
RDC  Drain contact resistance  Ohm  0 
RSC  Source contact resistance  Ohm  0 
IS  Bulk junction saturation current  A  1e14 
N  Bulk diode emission coefficient  1  
NDS  Reverse bias slope factor  1  
VNDS  Reverse slope transition voltage  V  1 
LD (DLAT, LATD)  Lateral diffusion for length  m  0 
WD  Lateral diffusion for width  m  0 
LDIF  Lateral diffusion beyond the gate  m  0 
HDIF  Heavily doped diffusion length  m  0 
XL (LDEL)  Masking and etching effects on L  m  0 
XW (WDEL)  Masking and etching effects on W  m  0 
LMLT  Length multiplier  1.0  
WMLT  Width multiplier  1.0  
SCALM  Model parameter scaling factor  1.0  
FC  Coefficient for the forwardbias depletion junction capacitance  formula  0.5 
CJGATE  Gate edge capacitance  F/m  CJSW 
CBD  Total zero bias BD junction capacitance  F  0 
CBS  Total zero bias BS junction capacitance  F  0 
JCAP  Depletion capacitance model selector  1  
BULK  Substrate node name 
Table 1: Standard SmartSpice MOSFET parameters.
Parameter  Description  Units  Default 

TEMPLEV  Temperature model  0  
TEMPLEVC  Temperature model for junction capacitance  0  
EG  Energy gap at 0K  eV  1.16 
GAP1  First bandgap correction factor  eV/K  7.02e4 
GAP2  Second bandgap correction factor  K  1108 
XT1  Saturation current exponent  3.0  
TCJ (TCJO, CTA, CTC)  Bottom junction capacitance temperature coefficient  1/K  0 
TVJ (TPB)  Bottom junction potential temperature coefficient  V/K  0 
TMJ1 (TM1)  Linear MJ temperature coefficient  1/K  0 
TMJ2 (TM2)  Parabolic MJ temperature coefficient  1/K2  0 
TCJSW (CTP)  Sidewall junction capacitance temperature coefficient  1/K  0 
TVJSW (TPHP, TPBSW)  Sidewall junction potential temperature coefficient  V/K  0 
TMJSW1  Linear MJSW temperature coefficient  1/K  0 
TMJSW2  Parabolic MJSW temperature coefficient  1/K2  0 
TTT1  Linear TT temperature coefficient  1/K  0 
TTT2  Parabolic TT temperature coefficient  1/K2  0 
TRD1 (TRD)  Linear temperature coefficient for drain resistance  1/K  0 
TRD2  Parabolic temperature coefficient for drain resistance  1/K2  0 
TRS (TRS1)  Linear temperature coefficient for source resistance  1/K  0 
TRS2  Parabolic temperature coefficient for source resistance  1/K2  0 
The options listed below are applied to the SmartSpice BSIM3v3 Level 8 model. These parameters can be specified in the .OPTIONS statement.
The options ACM, DEFL, DEFW, DEFAD, DEFAS, DEFPD, DEFPS, DEFNRD, DEFNRS, HDIF, LD, LDIF, SCALE, SCALM and TNOM are standard for all MOSFET models including BSIM3v3 Level 8.
The option BYPASS currently is unsupported for BSIM3v3.
The option CAPDC = 1 can be specified to calculate BSIM3v3 capacitances for both Level 8 and Level 81. Default 0 (OFF).
The option CONV = num ( 0 =< num <= 5 ) is supported for BSIM3v3. Default 0.
The conductance GMIN is connected in parallel with the bulkdrain and bulksource diodes. Default 1e12.
The conductance DCGMIN is connected between drain and source nodes. Default 0.
The option VZERO = num is applied to the BSIM3v3 Level 8 model. This option defines the MNA formulation in SmartSpice. The option VZERO = 2 is recommended when simulating relatively large circuits, with hundreds or thousands of transistors in the time domain. It accelerates simulation and in some cases increases the accuracy of simulation results. Default 0. For further information regarding the option VZERO, see "SmartSpice Version 1.4.0 Release Notes".
The option EXPERT = 1 can be used to detect discontinuities in the BSIM3v3 model. If EXPERT = 777 SmartSpice will detect negative conductances GM, GDS and GMBS, and negative capacitances. Default 0 (OFF).
For further information regarding the BSIM3v3 Level 8 implementation, see Application Notes: 1. "SmartSpice BSIM3 Version 3 Intrinsic Capacitance Models" 2. "SmartSpice BSIM3 Version 3 NonQuasi Static Model"
SECTION 2
Differences between BSIM3v3 Level 8 and Level 81 Parameters
The following junction current and capacitance parameters have different defaults in the SmartSpice (level 8) and Berkeley (level 81) BSIM3v3 models.
Parameter  Description  Units  Level 8  Level 81 

JS  Bulk junction saturation current per unit area  A/m2  0  1.0e4 
JSW  Sidewall junction saturation current per periphery length  A/m  0  
IS  Bulk junction saturation current  A  1.0e14  
CJ  Zero bias area capacitance per junction area  F/m2  0  5e4 
VJ (PB)  Bottom junction builtin potential  V  0.75  1 
CJSW  Zero bias sidewall capacitance per junction perimeter  F/m  0  5e10 
VJSW (PBSW, PHP)  Sidewall junction builtin potential  V  0.75  1 
Note : In the UC Berkeley implementation, the drain saturation current is calculated as follows;
if AD > 0 then DrainSatCurrent = JS * AD else DrainSatCurrent = 1.0e14
The parameters IS and JSW are not used.
SECTION 3
Additional Parameters in the SmartSpice BSIM3v3 model
Additional parameters were introduced into the SmartSpice level 8 model to resolve conflicting situations in the Berkeley BSIM3v3 implementation, and to improve the convergence properties of the BSIM3v3 model.
3.1 TEMPMOD Parameter
The UC Berkeley BSIM3v3 manual (final version) and implementation are not consistent in terms of the ni, fs and vbi temperature dependencies. In the source code they are calculated as functions of the nominal temperature tnom. In contrast the BSIM3v3 manual treats them as functions of the circuit temperature, temp.
In the SmartSpice level 8 model, ni, fs and vbi are calculated at tnom by default. This corresponds to the Berkeley implementation rather that the documentation. The temperature equations described in the Berkeley manual will be used if the model parameter tempmod=2.
3.2 Parameter Scaling
In the UC Berkeley BSIM3v3 implementation, some model parameters can be scaled depending upon actual parameter values. These parameters are U0, LU0, WU0, PU0, NPEAK, LNPEAK, WNPEAK, PNPEAK, NGATE, LNGATE, WNGATE and PNGATE.
U0, LU0, WU0 and PU0 Parameters
In the Berkeley BSIM3v3 source code, these parameters can be scaled in two routines, "b3mpar.c" and "b3set.c". In b3mpar.c the scaling is performed independently for each parameter as follows,
if U0 > 1 then U0 = U0 * 1e4; if LU0 > 1 then LU0 = LU0 * 1e4; if WU0 > 1 then WU0 = WU0 * 1e4; if PU0 > 1 then PU0 = PU0 * 1e4;
In b3set.c the binning parameters LU0, WU0 and PU0 are scaled depending upon the U0 value.
In the SmartSpice (level 8) implementation, scaling is performed using the following rule,
if U0 > 1 then LU0 = LU0 * 1e4; WU0 = WU0 * 1e4; PU0 = PU0 * 1e4; U0 = U0 * 1e4;
i.e. parameter scaling is based upon the basic U0 value.
NPEAK, LNPEAK, WNPEAK and PNPEAK Parameters
In the SmartSpice BSIM3v3 (level 8) implementation, these parameters are scaled as follows,
if NPEAK > 1e20 then LNPEAK = LNPEAK * 1e6 WNPEAK = WNPEAK * 1e6 PNPEAK = PNPEAK * 1e6 NPEAK = NPEAK * 1e6
NGATE, LNGATE, WNGATE and PNGATE Parameters
In the SmartSpice BSIM3v3 (level 8) implementation, these parameters are scaled as follows,
if NGATE > 1e23 then LNGATE = LNGATE * 1e6 WNGATE = WNGATE * 1e6 PNGATE = PNGATE * 1e6 NGATE = NGATE * 1e6
3.3 Smooth Function Parameters
The SmartSpice BSIM3v3 (level 8) model contains a number of smoothing functions that were developed to eliminate discontinuities in the Berkeley BSIM3v3 model. The model parameters used in these functions are listed below;
Parameter  Description  Units  Default 

ABULKLIM  Parameter of the Abulk smoothing function  0.01  
NLIM  Parameter of the n smoothing function  0.01  
LAMBLIM  Parameter of the Lambda and Ngate smoothing function  0.03  
UEFFLIM  Parameter of the Ueff smoothing function  0.5  
SMOOTH  Smoothing parameter flag  1 
The parameter ABULKLIM is used to prevent a discontinuity due to the limitations Abulk0 >= 0.01 and Abulk >= 0.01. The disable the Abulk smoothing function let ABULKLIM = 0.0.
The parameter NLIM is used to prevent a discontinuity for n >= 1 in the subthreshold swing parameter n equation. To disable the n smoothing function let NLIM = 0.0.
The parameter LAMBLIM is used to prevent a discontinuity for l <= 1 in the equation
(lambda) = A1 . Vgsteff + A2
and in the polysilicon depletion effect (Ngate) equation. To disable both the Lambda and Ngate smoothing functions let LAMBLIM = 0.0.
The parameter UEFFLIM is used to prevent the denominator in both the meff and Abulk equations from becoming negative. The meff smoothing function cannot be disabled.
By setting the smoothing parameter flag, SMOOTH, equal to 0, all smoothing functions except for the meff smooth ing function will be disabled.
SECTION 4
Output Device Variables
Variable  Definition  Variable  Definition 

cd (id)  Drain Current  gbd  Bulk to drain conductance 
cs  Source Current  gbs  Bulk to source conductance 
cg  Gate Current  gm  DS transconductance controlled by Vgs 
cb  Bulk Current  gmbs  DS transconductance controlled by Vgs 
ibd  Bulkdrain junction current  gds  DS transconductance controlled by Vds 
ibs  Bulk source junction current  sourceconduct  Source conductance 
vbs  Source to bulk voltage  drainconduct  Drain conductance 
vds  Drain to source voltage  vgs  Gate to source voltage 
vdsat  Saturation drain voltage  vth  Threshold voltage 
Variable  Definition  Variable  Definition 

capbd  Bulkdrain capacitance  qg  Total gate charge 
capbs  Bulksource capacitance  cqg  Gate capacitance current 
capgbo  Gatebulk overlap capacitance  qd  Total drain charge 
capgso  Gatesource overlap capacitance  cqd  Drain capacitance current 
capgdo  Gatedrain overlap capacitance  cggb (cgg)  Charge conservation model term 
capgg  Total gate capacitance  cgdb (cgd)  Charge conservation model term 
qbulk  Channel bulk charge  cgsb (cgs)  Charge conservation model term 
qgate  Channel gate charge  cdgb (cdg)  Charge conservation model term 
qdrain  Channel drain charge  cddb (cdd)  Charge conservation model term 
qbd  Bulkdrain charge  cdsb (cds)  Charge conservation model term 
qbs  Bulksource charge  cbgb (cbg)  Charge conservation model term 
qb  Total bulk charge  cbdb (cbd)  Charge conservation model term 
cqb  Bulk capacitance current  cbsb (cbs)  Charge conservation model term 
SECTION 5
BSIM3v3 Level 8 Capacitance Model
The capacitance model in the SmartSpice BSIM3v3 (level 8) model is evaluated in three steps.
 The variable gate, bulk and drain charges,
qg, qb and qd respectively, are calculated as functions of the
gate, drain, source and bulk voltages. The charge contribution
of the overlap, bulkdrain and bulksource capacitances are not
added to qg and qb at this stage. The partitioning ratio of qd
to qs is determined using the XPART model parameter. Nine basic
"capacitances" (partial derivatives of the qg, qd and qb charges
with respect to Vgb, Vdb and Vsb) are calculated as follows;
[EQUATION MISSING]
 The total gate, drain and bulk charges (Qg,
Qd and Qb respectively) are calculated. These charges con tain
the variable gate (qg), drain (qd) and bulk (qb) charges as well
as the charge contribution of the over lap, bulkdrain and bulksource
capacitances.
 Sixteen derivatives of the terminal charges
with respect to the terminal voltages are computed as follows;
[EQUATION MISSING]
where n and m are gate, source, drain or bulk.
These derivatives are used as transcapacitances for small signal AC analysis.
The following BSIM3v3 device parameters can be stored, printed and/or measured using the .save, .probe, .print and .measure statements.
 The variable transcapacitances,
cggb
cdgb
cbgb
cgdb
cddb
cbdb
cgsb
cdsb
cbsb
 The variable bulkdrain and bulksource
capacitances
capbd and capbs  The total gate, drain and bulk charges
Qg, Qd and Qb
capgdo, gatedrain overlap capacitance
capgso, gatesource overlap capacitance
capgbo, gatebulk overlap capacitance
capgg, total gate capacitance
where capgg = cggd + capgdo + capgso + capgbo
Note: To output capacitances during .DC analysis, let the optional parameter capdc = 1 in the .options statement.
SECTION 6
Example
Input Deck
* UC Berkeley BSIM3 Version 3 Model * Model parameter set obtained from * http://rely.eecs.berkeley.edu:8080/bsim3www/bsim3.htm .OPTIONS RELTOL=1e4 ABSTOL=1e16 VNTOL=1e9 .OPTIONS CAPDC=1 NUMDGT=9 FORMAT NOMOD .SAVE + @mn1[vth] @mn1[vdsat] @mn1[gm] @mn1[gds] @mn1[gmbs] + @mn2[vth] @mn2[vdsat] @mn2[gm] @mn2[gds] @mn2[gmbs] + @mn1[cggb] @mn1[cgdb] @mn1[cgsb] @mn1[cdgb] @mn1[cddb] + @mn1[cdsb] @mn1[cbgb] @mn1[cbdb] @mn1[cbsb] + @mn3[cggb] @mn3[cgdb] @mn3[cgsb] @mn3[cdgb] @mn3[cddb] + @mn3[cdsb] @mn3[cbgb] @mn3[cbdb] @mn3[cbsb] *=================================================================== .DC VGG 0 5v 0.05 Vgg gg 0 DC 3 Vdd dd 0 DC 0 Vbb bb 0 DC 0 * SmartSpice BSIM3V3 (Level 8) model; Vds=5V Vb b bb DC 0 Vd d dd DC 5v Vs s 0 DC 0 Vin g gg DC 0 Mn1 d g s b NMOS w=4.0u l=0.8u + PS=19.50u AS=17.10p PD=19.50u AD=17.10p * UC Berkeley BSIM3v3 (Level 81) model; Vds=5V Vb2 b2 bb DC 0 Vd2 d2 dd DC 5v Vs2 s2 0 DC 0 Vin2 g2 gg DC 0 Mn2 d2 g2 s2 b2 NMOS81 w=4.0u l=0.8u + PS=19.50u AS=17.10p PD=19.50u AD=17.10p * SmartSpice BSIM3V3 (Level 8) model; Vds=1V Vb3 b3 bb DC 0 Vd3 d3 dd DC 1 Vs3 s3 0 DC 0 Vin3 g3 gg DC 0 Mn3 d3 g3 s3 b3 NMOS w=4.0u l=0.8u + PS=19.50u AS=17.10p PD=19.50u AD=17.10p * UC Berkeley BSIM3v3 (Level 81) model; Vds=1V Vb4 b4 bb DC 0 Vd4 d4 dd DC 1 Vs4 s4 0 DC 0 Vin4 g4 gg Dc 0 MN4 d4 g4 s4 b4 NMOS81 w=4.0u l=0.8u + PS=19.50u AS=17.10p PD=19.50u AD=17.10p .LET kirhNplus='i(vin)+i(vs)+i(vd)+i(vb)' .LET kirhNminus='i(vin2)+i(vs2)+i(vd2)+i(vb2)' .LET kirhPplus='i(vin3)+i(vs3)+i(vd3)+i(vb3)' .LET kirhPminus='i(vin4)+i(vs4)+i(vd4)+i(vb4)' .MEASURE DC max_kirhNplus MAX `abs(kirhNplus)' .MEASURE DC max_kirhNminus MAX `abs(kirhNminus)' .MEASURE DC max_kirhPplus MAX `abs(kirhPplus)' .MEASURE DC max_kirhPminus MAX `abs(kirhPminus)' * ****** SmartSpice BSIM3V3 (Level 8) model * .MODEL NMOS NMOS level=8 + Tnom=27.0 + nch= 1.024685E+17 tox=1.00000E08 xj=1.00000E07 + lint= 3.75860E08 wint=2.02101528644562E07 + vth0= .6094574 k1= .5341038 k2= 1.703463E03 k3=17.24589 + dvt0= .1767506 dvt1= .5109418 dvt2=0.05 + nlx= 9.979638E08 w0=1e6 + k3b= 4.139039 + vsat= 97662.05 ua=1.748481E09 ub= 3.178541E18 uc=1.3623e10 + rdsw= 298.873 u0= 307.2991 prwb=2.24e4 + a0= .4976366 + keta=2.195445E02 a1= .0332883 a2= .9 + voff=9.623903E02 nFactor= .8408191 cit= 3.994609E04 + cdsc= 1.130797E04 + cdscb=2.4e5 + eta0= .0145072 etab=3.870303E03 + dsub= .4116711 + pclm= 1.813153 pdiblc1= 2.003703E02 pdiblc2= .00129051 pdiblcb=1.034e3 + drout= .4380235 pscbe1= 5.752058E+08 pscbe2= 7.510319E05 + pvag= .6370527 prt=68.7 ngate=1.e20 alpha0=1.e7 beta0=28.4 + prwg=0.001 ags=1.2 + dvt0w=0.58 dvt1w=5.3e6 dvt2w=0.0032 + kt1=.3 kt2=.03 + at= 33000 + ute=1.5 + ua1= 4.31E09 ub1= 7.61E18 uc1=2.378e10 + kt1l=1e8 + wr=1 b0=1e7 b1=1e7 dwg=5e8 dwb=2e8 delta=0.015 + cgdl=1e10 cgsl=1e10 cgbo=1e10 xpart=0.0 + cgdo=0.4e9 cgso=0.4e9 + clc=0.1e6 + cle=0.6 + ckappa=0.6 * ***** UC Berkeley BSIM3v3 (Level 81) model * .MODEL NMOS81 nmos level=81 + Tnom=27.0 + nch= 1.024685E+17 tox=1.00000E08 xj=1.00000E07 + lint= 3.75860E08 wint=2.02101528644562E07 + vth0= .6094574 k1= .5341038 k2= 1.703463E03 k3=17.24589 + dvt0= .1767506 dvt1= .5109418 dvt2=0.05 + nlx= 9.979638E08 w0=1e6 + k3b= 4.139039 + vsat= 97662.05 ua=1.748481E09 ub= 3.178541E18 uc=1.3623e10 + rdsw= 298.873 u0= 307.2991 prwb=2.24e4 + a0= .4976366 + keta=2.195445E02 a1= .0332883 a2= .9 + voff=9.623903E02 nFactor= .8408191 cit= 3.994609E04 + cdsc= 1.130797E04 + cdscb=2.4e5 + eta0= .0145072 etab=3.870303E03 + dsub= .4116711 + pclm= 1.813153 pdiblc1= 2.003703E02 pdiblc2= .00129051 pdiblcb=1.034e3 + drout= .4380235 pscbe1= 5.752058E+08 pscbe2= 7.510319E05 + pvag= .6370527 prt=68.7 ngate=1.e20 alpha0=1.e7 beta0=28.4 + prwg=0.001 ags=1.2 + dvt0w=0.58 dvt1w=5.3e6 dvt2w=0.0032 + kt1=.3 kt2=.03 + at= 33000 + ute=1.5 + ua1= 4.31E09 ub1= 7.61E18 uc1=2.378e10 + kt1l=1e8 + wr=1 b0=1e7 b1=1e7 dwg=5e8 dwb=2e8 delta=0.015 + cgdl=1e10 cgsl=1e10 cgbo=1e10 xpart=0.0 + cgdo=0.4e9 cgso=0.4e9 + clc=0.1e6 + cle=0.6 + ckappa=0.6 .END
Measurement Results
* UC Berkeley BSIM3 Version 3 model DC Analysis, 27 deg C,Fri Mar 29 10:03:27 1996 max_kirhnplus = 9.051605833e19 at= 3.700000000e+00 max_kirhnminus = 5.000000956e12 at= 3.250000000e+00 max_kirhpplus = 7.999465181e19 at= 4.950000000e+00 max_kirhpminus = 1.000000639e12 at= 5.000000000e+00
Figure 1: Comparison of ids vs vds curves obtained using the SmartSpice BSIM3v3 level 8 and level 81 models.
This plot contains two sets of ids vs vds curves, the first obtained with vds = 5V and the second obtained with vds = 1V. As can be seen, there is no discernible difference between the curves gener ated using the level 8 BSIM3v3 model and the original UC Berkeley BSIM3v3 model (i.e. level 81) in SmartSpice.
This plot contains gm vs vgs curves obtained from two transistors (mn1 and mn2). These transistors have exactly the same bias conditions. The mn1 transistor uses the SmartSpice BSIM3v3 level 8 model, while the mn2 transistor uses the original UC Berkeley model (i.e. level 81). As can be seen a discontinuity exists in the original Berkeley model and this discontinuity has been removed from the SmartSpice BSIM3v3 level 8 model.
This plot contains the curves generated by some of the capacitance output variables in the Smart Spice BSIM3v3 level 8 model.