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TCAD

Analog / AMS / RF

	   Overview
	   Gateway
	   SmartSpice
	   Verilog-A Language
	   SmartSpiceRF
	   Harmony
	   UTMOST III     
	   UTMOST IV     
	   SPAYN     
  

Custom IC CAD

	   Overview
	   Expert
	   Guardian
	   HIPEX
	   ClarityRLC
  

Interconnect Modeling

	   Overview
	   EXACT
	   QUEST
	   CLEVER
	   STELLAR
  

Digital CAD

	   Overview
	   SILOS
	   HyperFault
	   AccuCell
	   AccuCore
	   CatalystAD
	   CatalystDA
	   Spider
  

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Download & Support Supported Platforms

Licensing

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	  TCAD Unlimited
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	  Perpetual	  
	  EDA Academic Suite	  
	  

PDK Design Flows

	  Overview
	  Available PDKs
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	  PDK Development Services
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	  Migration to Silvaco PDKs  

Technical Library

  EDA Publications  
  TCAD Publications  
  Video Library

Services

	   Overview
	   TCAD Services
	   SPICE Modeling
	   Parasitic Extraction
	   PDK Development
	   Cell Libraries and Blocks
  

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Presentation Materials

Digital CAD

Logic and Fault Simulation - HyperFault, SILOS

Cell / Core Characterization - AccuCell, AccuCore

Place and Route - Spider