Contents:

• Introduction
• Process simulation requirements
• Device simulation requirements
• Case study
• Layout of P+/N+ well boundary
• Mask edges and grid for 2D cross section of layout
• Final process structure with junctions
• Final process structure with doping and depletion regions
• Device simulation model requirements
• Transient device simulation setup
• Current vs. time during transient latchup
• Comparison of 1ns and 3ns duration pulses
• Flowlines in structure during Vss pulse
• Flowlines in latched structure
• DC latchup simulation setup
• Positive DC bias on Vdd
• Parasitic vertical pnp bipolar characteristic
• Negative DC bias on Vss
• Parasitic lateral npn bipolar characteristic
• P+/N+ spacing
• Overlay of two structures with different p+/n+ spacings
• Comparison of positive DC latchup characteristics
• Conclusion

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