Silvaco - Experts Netlist Driven Layout

Expert features a powerful Netlist Driven Layout (NDL) function to assist the user in creating a layout. It increases the productivity of layout design by automating cell generation and providing visual cues to assist in the wiring process. In this example, a latch circuit layout will be built based on developed child cells.

Open <latch.eld> project file from Expert. In this project, there are some cells (such as INVX, MNL, MPL) etc developed and ready to be used to generate the latch circuit. See Figure 1.

Figure 1. Loading project that includes child cells.
Make sure that NDL options ‘Show Nets’, ‘Show Pins’ and ‘Show Ports’ are ON from ‘Tools–>Netlist Driven Layout’ or toolbar.
Use ‘Tools‡NDL‡Load Netlist’ to load Gateway netlist <latch1.net>.
Click ‘+’ in the Netlist Rover sub-panel from Netlist Panel, i.e. Netlist Editor Window to expand circuit hierarchical tree. See Figure 2.

Figure 2. Importing Netlist.
Select “MNL” in the tree, then click right mouse button to open pop-up menu. There already is a cell “MNL” in this project, so users can click on ‘Open’ to see the P-cell with default parameters and corresponding XI-script (displayed in separate window). The cell has two Metal1 pins D and S, and Poly box assigned pin G.
Select cell “INVX” in the circuit hierarchical tree, and click right mouse button. Select ‘Open’ in pop-up menu to open existing view “INVX” and inspect its pins. Switch from ‘Flat View’ into ‘Lazy View’ via ‘View‡ Cell View‡ Lazy’ or from Hierarchy toolbar to see ports in instances MPL (MI0) and MNL (MI1). See Figure 3.

Figure 3. Viewing of circuit element with ‘Open’ command from Netlist Rover.
Select cell “top” in the netlist hierarchy tree. As there is no cell “top” in the project as shown in Figure 3, the user has to right mouse click to activate the pop-up menu with ‘Open’, ‘Create’ and ‘Map’.
‘Map’ command opens a dialog which allows setting correspondence between model name (or subcircuit name) in netlist with cell name in layout. Also, if the user would like to use standard cell(s) e.g. INVX from another library/project e.g. “standardlib” instead of current work library/project, please key in following syntax (Figure 4):

Lib/Prj_name_of_cell::cell_name

Note that library “standardlib” should be an active library/project, which can be set from ‘Expert–>Library–>Set up’. For this example no mapping is necessary, since the user is using child cells from the same library/project.

Figure 4. Mapping subcircuits/devices to the cells from the other library/project.
Click right mouse button at “top” again, then select ‘Create’ command in the popup menu. NDL tool uses cells that are already in the project MNL, MPL, INVX and INVX1 to create new cell “top”. MNL and MPL are P-cells, whose instance parameters L and W are selected based on netlist <latch.net>. See Figure 5.

Figure 5. Initial placement with highlighted nets.
Note that the default cell name “top” can be changed at will. Before creating the circuit layout, in the netlist panel, right click “top” and select ‘Map’ in pop-out menu, key in any preferred cell name (e.g. “latch”). If the user would just like to create this circuit within the current working directory, there is no need to key in the library name since the default parent project will be the current working directory. See Figure 6.

Figure 6. Assigning the generated cell a meaningful name in current project.
After the NDL run, the new cell “top” (or the cell name just chosen by ‘Map’ command) opens automatically. Expert shows flight lines to indicate which pins belong to the same net and should be connected to each other, as seen in Figure 5.

Next, the user may need to compare instances names and parameters in layout with netlist data, and inspect connectivity info which are represented by flight lines, and compare with net names in the netlist. Following functions can be used during inspection.

•	To switch views, perform ‘View –> Cell View –> Flat / Lazy’. In Lazy view ports of cell instances appear in dashed lines.
•	Blue flight lines indicate internal nets, external connections are yellow.
•	‘Tools –> NDL –> Show Global Nets’ shows green flight lines for global nets VDD and VSS connections. Global nets have a lot of connections; therefore turning its visibility off decreases the congestion of flight lines and simplifies design editing.
•	Note that cells MPL and MNL do not have VDD and VSS pins, so global flight lines end at the cell instance bounding box.

To improve initial placement, select Move/Flip/Rotate at any instance. Meanwhile the user can manage nets of generated layout via ‘Tools –>NDL –>Nets’. Add connections as indicated by the flight lines.
Edit the cell “top” until it looks like the following Figure 7, which has improved placement and wiring added. Till this point the layout may appear messy. To avoid this, the user can check ‘Tools –> NDL –> Unfinished Nets Only’, then press ‘Update Connectivity’ or use ‘Reextract’ button in NDL tool bar to show flight lines that include unconnected pins.

Figure 7. Edited Layout view before re-extraction.
‘Tools –>NDL –>Closest Points Only’ shows parts of unfinished nets that represent missing connections (use ‘Update Connectivity’ or ‘Reextract’ to update display). With this feature, Expert NDL can provide users with updated connectivity from time to time, assisting user to finish the connectivity. It can be seen from Figure 7 and Figure 8 that the connectivity has been updated after reextraction.

Figure 8. Edited Layout view after re-extraction to show Unfinished Nets Only.
Add a box in Metal1 on the left to intentionally short nets ‘X’ and ‘1_A’ as seen in Figure 9. After ‘Reextract’ or ‘Update Connectivity’, flight lines for both nets ‘X’ and ‘1_A’ displayed in red.

Check option ‘Tools –>NDL –>Show Shorted Nets Only’ to show flight lines for shorted nets only to simplify looking for shorts and fixing the problem nets.

Figure 9. Edited Layout view after re-extraction to show ‘Shorted Nets Only’.
Continue to clear unfinished nets and shorted nets, if any. The layout view after having rectified above-mentioned unfinished and shorted connections is shown in Figure 10.

To read more about Netlist Driven Layout feature, user may refer to Expert and ExpertView User Manual. If the reader would like to have these demo files (i.e. netlist, Expert .eld files, etc), please contact the nearest local Silvaco support team.

Figure 10. After having rectified unfinished and shorted connections.

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