New Ferroelectric Capacitance Model frmc from Ramtron Corporation in SmartSpice

Introduction

Ramtron International Corporation has developed a ferroelectric capacitance model with a new concept of double distributions of domain reversal voltages.

The model is now available in the public domain. It has been implemented in SmartSpice and can be invoked by setting LEVEL=6 in the capacitance model card. The previous model is also implemented in SmartSpice and can be invoked by setting LEVEL=5 in the capacitance model card.

Features

The ferroelectric capacitor is treated as a nonlinear capacitor, except the biases in the ferroelectric materials are reversed at reversal voltages with double distributions. The model has been tested under various combinations of input voltage waveforms. Compared to the previous model (LEVEL=5), this model is much more accurate in ferroelectric hysteresis loops and voltage pulse responses, its simulation speed is at least six times faster than the previous interpreter model, and the temperature dependence is included. Furthermore, the parameters in frmc can be easily extracted.

Ferroelectric Capacitor Device

Syntax form

Cxxx n1 n2 mname <IC=val> <L=val> <W=val> <IP=val> <A=val>

Output Device Variables

Ferroelectric Capacitor Model

Syntax form

.MODEL mname C LEVEL=6 <parameter=value>

New Model Parameters

Simulation Results

Before showing results obtained with the new ferroelectric capacitance model frmc (LEVEL=6), some simulation results are presented to show the limitations of the previous model (LEVEL=5). The previous model LEVEL=5 is successful in modeling the major hysteresis loops under continuous sinusoid and triangular input voltages but, the major hysteresis loops become unrealistic when the capacitor is driven by voltage pulses. To illustrate this the input waveform shown in Figure 1 was applied to a circuit containing a ferroelectric capacity shown in Figure 2. When the capacitor models were LEVEL=5 large jumps can be observed at three points (0V, +/- 5V) on the hysteresis loops shown in Figure 3, This means that the charge on the ferrocapacitance still increases even when the input voltage is set at 5V. This phenomenon is not observed in real ferro-electric capacitors. This discrepancy is due to the incorrect modeling for the domain reversal behavior.

Figure 1. Input pulse voltage waveform

Figure 2. Sawyer-Tower circuit at hystersis loop measurement

Figure 3. Hysteresis loops under input pulse voltage waveform

The ferroelectric capacitance model frmc has been modified to consider relatively large voltage oscillations which are just across the coercive field. The new model has passed tests on large circuit simulations with various voltage oscillations.

The new ferroelectric capacitance model (LEVEL=6) has corrected the previous problems with stepped waveforms. The same circuit shown in Figure 2 was applied to test the new model.

First a sinusoidal input waveform was applied which resulted in the output waveform shown in Figure 4. The hysteresis loops under the sinusoidal voltage at 1 MHz are correct. Next an input voltage step shown in Figure 5 was applied. Figure 6 shows the hysteresis loops obtained which are now clearly correct. Further, an unwanted peak was also present in the input pulse of Figure 5. Its influence can be observed on the hysteresis loop of Figure 6 which is again correct. Finally, to test the new model to the extreme the input voltage waveform shown in

Figure 4. Hysteresis loops under sinusoidal voltage form at 1MHz frequency.

Figure 5. Input pulse voltage waveform with widths of several ns

Figure 6. Hysteresis loops under pulse voltage waveform

Figure 7 was applied. The output waveform shown in Figure 8 shows the correct hysteresis behavior even under these extreme conditions.

Figure 7. Input voltage with unwanted oscillations

Figure 8. Hysteresis loops from unwanted oscillations

Conclusion

The previous ferroelectric capacitance model (LEVEL=5) unrealistically simulates ferroelectric subloops and voltage pulse responses. Thus, it is dangerous to apply for simulations at low voltage or voltage pulse responses.

The new ferroelectric capacitance model frmc (LEVEL=6), based on double distributions of domain reversal voltages, provides accurate simulation for ferroelectric hysteresis loops and sub-loops, transient responses to short voltage pulses (with widths in the nanosecond range), and temperature behavior of ferroelectric capacitors. The advantages can be summarized as:

• The new model is accurate and reliable for any applied voltage waveforms and voltage levels. The applied voltages can be short pulses at the nanosecond scale.
• The simulation speed is at least six times faster than the previous interpreter model.
• The new model does not need gap capacitors and resistors. From the user's point of view, it is a two-terminal device; thus, it is easy to use.
• The parameters in frmc can be easily extracted.
• The temperature dependence has been included in the model.

References

1. Ramtron International Corporation documents