Simulation Standard - 1999

Volume 10, Number 1, January 1999

PHILIPS Model 9 New MM9 Extraction Routine in UTMOST III

New Built-in Dichotomic Search Algorithm in SmartSpice

Enhanced Statistical Features in SPAYN Version 1.7.2

New Parameters for TFT model: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT

Hints & Tips

Volume 10, Number 2, February 1999

New, Fast Numerical Algorithm for Diffusion Modeling Implemented in ATHENA Version 5.0

Mixed Circuit Device Simulation of Single Event Upset in a Memory Cell

Volume 10, Number 3, March 1999

Introducing Guardian - LVS Verification for PC-based Platforms

Advanced Pairwise Merging Algorithm for VLSI Floorplanning

Hints & Tips

Volume 10, Number 4, April 1999

Intrinsic Capacitance Parameter Extraction in UTMOST III

Mixed-Signal Simulation with SmartSpice in the Cadence Design Framework II

SPAYN: Golden Device Search Algorithm, EKV MOSFET Model and Improved GUI

Hints & Tips

Volume 10, Number 5, May 1999

Very Low Energy Boron Implant Simulation Using New BCA Monte-Carlo Model

Continous Trap Model for Accurate Device Simulation of Polysilicon TFTs

Circuit Performance Analysis of Multiple ATHENA Transistors Using MixedMode

Hints & Tips

Volume 10, Number 6, June 1999

Maverick- Hierarchcal Full-Chip Extractor

Hints, Tips and Solutions

Volume 10, Number 7, July 1999

New SOI UTMOST Module

MOS31 JFET/MOSFET Model Now Available in SmartSpice

Hints & Tips

Volume 10, Number 8, August 1999

Generating a Capacitance Coefficient Database for any Chip Level LPE Tool Using EXACT

New Thermionic Emission and Tunneling Models in ATLAS

High Performance ATHENA and ATLAS Simulation on PC under NT

Hints & Tips

Volume 10, Number 9, September 1999

Scholar: An Enhanced Multi-Platform Schematic Capture

Hints & Tips

Volume 10, Number 10, October 1999

BSIM3SOI Version 2.1 (FD, DD and PD) Models Released in SmartSpice

New Improvements in TFT Models: Amorphous (Level=35) and Poly-Silicon (Level=36) TFT

Hints & Tips

Volume 10, Number 11, November 1999

The Industry Standard of SOI Technology From Process To Circuit Simulation

Optoelectric Device Simulation of a Dual-Base BJT Using Luminous

Modelling Tunneling Currents in Ultra Thin Oxides

Modeling Bidirectional Thyristors Using ATLAS

Hints & Tips

Volume 10, Number 12, December 1999

An Intuitive Front-End to Effective and Efficient Schematic Capture Design

Hints & Tips