Release of RPI Amorphous Silicon and Polysilicon
TFT Models in SmartSpice and UTMOST

Introduction

Thin film transistors (TFTs) have an important application in the manufacture of active matrix LCD displays. As this technology has become more mature, a number of different models of both amorphous silicon (a-Si) and polysilicon TFTs have been proposed. Recently two new models developed by the Rensselaer Polytechnic Institute (RPI) have been implemented in the SmartSpice circuit simulator. These models are also now available in the TFT module of UTMOST III and this article will discuss the different model characteristics, and their use in both SmartSpice and UTMOST III.

Description

Due to the lack of commercial quality TFT models, designers typically approximate the behaviour of the TFT device using standard MOSFET models. With decreasing device geometries this approach is no longer suitable. While TFT devices can essentially be thought of as MOSFETs without a substrate contact, i.e. a three terminal device, the most significant physical difference occurs in the band structure of the thin film.

In crystalline silicon the structure has well defined conductance and valence bands. In both the a-Si and polysilicon lattices, the bandgap is populated with localized trap states. These trap states are due to the non-periodic nature of the lattice in a-Si and in the case of polysilicon due to trap states produced at the boundaries of each crystalline grain. Some of the physical effects affected by the presence of localized trap states are the field-effect mobility, subthreshold and leakage currents and the frequency dispersion of capacitance.

Amorphous TFT Model

The a-Si TFT models is available in SmartSpice as a LEVEL=35 MOSFET model. Each device has three terminals, drain, gate and source. The bulk node is not present. The model parameters that are specific to the a-Si TFT model are given in Table 1.

Parameter	Symbol	Description	Parameter	Symbol	Description
VTO [V]	VT0	Threshold Voltage	VFB [V]	VFB	Flat-band Voltage
GAMMA		Power Law Mobility Parameter	V0 [V]	V0	Characteristic Voltage of Deep States (Optimized)
VAA [V]	VAA	Characteristic Voltage for µFET	IOL [A]	IOL	Zero Bias Leakage Current
ALPHASAT	SAT	Saturation Parameter	VDSL [V]	VDSL	Vds Leakage Dependence
LAMBDA [V-1 ]		CLM Parameter	VGL [V]	VGL	Vds Leakage Dependence
MSAT	mSAT	Knee Shape Parameter	SIGMA0 [A]	0	Minimum Current
MUBAND	µn	Band Mobility: 0.001m2 /V/s	EPSI	i	Relative Permittivity of Gate Insulator: 7.4
G0	g0	Midgap DOS: 1.0 x 10 m eV	EPS	s	Relative Permittivity of Amorphous Silicon: 11
DEFO	dEF0	Dark Fermi Level Position: 0.6eV	NC	NC	Effective Conduction Band Band DOS: 3x10 m

Table 1 : Parameters specific to the a-Si TFT model.

The equivalent circuit for this model is given in Figure 1. As can be seen the circuit is similar to that of a basic MOSFET, with the bulk node and its associated elements removed. The Ids current has a number of regions, leakage, subthreshold and above threshold. The leakage current is modeled empirically at large negative biases and is generally quite small.

Figure 1. Equivalent circuit for the a-Si TFT model

In the subthreshold regime, most of the electron carriers are trapped in energy states, and as a consequence, the sheet electron concentration can be related to material parameters and the density of these states. This relationship is then used to derive the subthreshold current.

Above threshold, the sheet electron concentration is given by the modified charge control model. At threshold, carriers induced in the thin film are still trapped in the bandgap traps and the current flowing in the device will still be relatively small. As the free charge increases with increasing Vgs, the device will eventually turn on, but this Von will be greater than the threshold voltage Vt. This is not the case with standard MOSFET models. This effect results in a gradual transition between the exponential and linear regions. This effect is taken into account in the above threshold current model, by manipulating the field effect mobility.

Polysilicon TFT Model

The polysilicon TFT model is available in SmartSpice as a LEVEL=36 MOSFET model. Each device has three terminals, drain, gate and source. The bulk node is not present. The model parameters that are specific to the polysilicon TFT model are given in Table 2.

* Optimized Only

Table 2 . Parameters specific to the polysilicon TFT model.

The equivalent circuit for this model is given in Figure 2. As can be seen this model differs from the equivalent circuit for the a-Si device in that two resistors are added in series with the gate-source and gate-drain capacitances. These resistors are used to account for dispersion of capacitances with frequency, their value is a function of the channel resistance.

Figure 2. Equivalent circuit for the polysilicon TFT model

The polysilicon TFT model differs from the a-Si model in that a larger leakage current can exist. This current is a function of the thermionic field emission of carriers through grain boundary trap states. The leakage current a function of temperature, Vfb and the terminal voltages. It is independent of Vt and L. The expression for the leakage current also accounts for drain induced barrier lowering.

In the subthreshold region, the drain current can be effectively modeled using standard MOSFET theory. Above threshold, the current is subject to same effects as in the a-Si case, as discussed previously. In addition, trap states cause the kink effect. This effect is seen at high drain biases with the device biased in saturation.

Device Characterization

The TFT module of UTMOST III has been modified to support both of these models. Models for both a-Si and polysilicon devices have been extracted and the operation of the models verified against the measured data. Subsequently transient simulation using SmartSpice can been used to verify the effectiveness and accuracy of the I-V and C-V models. Typically a very good match exists between the measured and simulated results.

References

[1] Michael S. Shur, H. C. Slade, et al., "Modeling and scaling of a-Si:H and Poly-Si Thin Film transistors", MRS Spring Meeting, San Francisco, March 31-April 4, 1997.

[2] Michael S. Shur, Mark D. Jacunski, et al., "SPICE models for amorphous silicon and polysilicon thin film transistors", Elec. Chem. Soc. Proc., Vol 96-23, pp 242-259, 1996.