A novel Parallel Solver, coupled with the Six Equation Solver, uniquely positions ATLAS as the premier 2D device simulation tool. A significant number of new features and improved physical models address simulation needs for deep sub-micron CMOS and a large array of complex III-V device structures. A complete simulation solution for emerging FRAM technology is also included in this release.

Figure 1. Scaling efficiency for parallel ATLAS on six examples.

Parallel ATLAS

This release of ATLAS includes the ability to take full advantage of multiprocessor machines. A singe job can be run on more than one CPU. Typical efficiency is about 75% so that a job running on 4 processors runs three times as fast a it would on a single processor. Longer more complex jobs are more efficient as more time is spent in the solver. A typical speed up is seen in Figure 1. All 2D applications within ATLAS are supported by the parallel solver [1]. Platforms currently supported are SGI, Sun Solaris2 and Convex (HP).

Updated MOS and Bipolar Physical Models

Klaassen's Mobility Model
-separate majority and minority mobilities
-all scattering processes included such as carrier- carrier scattering and screening.
Klaassen's Band Gap Narrowing Model
Shirahata Mobility Model
-tuned for moderate to heavy doped
MOS transistors
Modified Watt Model

Klaassen's mobility and band gap narrowing models have been shown to be more accurate for modeling the minority carrier mobility in the base of bipolar transistors [2][3]. This model is now included in ATLAS.

An extension to this model allows it to be used for MOSFETs. The Shirahata Mobility model[4] which describes the transverse field dependent mobility in MOS channels can be combined with Klaassen's model to provide a complete description of mobility in medium to heavily doped MOSFETs.

An enhancement has been made to the Watt mobility model (SURFMOB) to allow the model to be applied at nodes beyond the silicon surface. Users can choose the depth of action of the model. A constant transverse electric field is assumed over this depth. This leads to less mesh dependence of surface mobility.

Updated Features for Flash EEPROM Simulation

Non-local Concannon Model for hot electron injection, band-band tunneling and impact ionization
Allow addition of external capacitors between electrodes. This is used to model the coupling capacitance between the floating and control gate. Typically this capacitance is a 3D effect would otherwise be impossible to incorporate into a 2D simulation
Floating gates allowed in MixedMode

The application of a non-local model for the gate current is important for sub-micron Flash memory devices. The drift-diffusion based models are known to overestimate the amount of impact ionization in the device. A new model developed at NMRC Ireland using data from SGS-Thomson is included in this release.[5] For non-volatile memories the 3D nature of the capacitance between the floating gate and other electrodes needs to be accounted for. Although running 3D simulations using Device3D is a possibility a faster approach is to attach lumped capacitance's between the floating gate and other electrodes (typically the control gate) to control the coupling ratio. Figure 3 gives an example of the use of this external capacitance on device threshold. In many cases it is useful to look at the circuit performance of EPROM devices. This can be done using MixedMode in this release as a new algorithm for incorporating floating nodes into the mixed device/circuit simulation has been developed.

Figure 2. Concannon gate current model showing both electron and hole injection forming the gate current.

Figure 3. Effect of coupling capacitance variation of EEPROM characteristics.

Models for Ferroelectric materials used in FRAM technology

New Model for field dependent permittivity
Model for dielectric polarization
Built-in electric field history to allow simulation of hysteresis

Research groups around the world have been investigating the possibility of using ferroelectric materials such as PZT as dielectrics in future memory technologies. Ferroelectric capacitors and FRAM transistors are under development. To meet this need ATLAS includes models for ferroelectric behavior. It is able to account for field dependent permittivity and the polarization effects that lead to hysteresis in the switching curves. Figure 4 shows an example of hysteresis in an FRAM transistor.

Figure 4. Hysteresis in a FET made using a ferroelectric material. A Vt shift is seen due to the polarization of the ferroelectric gate insulator.

Improvements in Ionization Integrals

Allow better user control of the starting points for the electric field lines. The user can choose an offset voltage between the voltage on the contact being ramped and the contour of potential along which the field lines will start
Allow output of electric field lines to TonyPlot

Enhancements have been made to the existing algorithm for using ionization integrals to quickly estimate the breakdown voltage of devices. The method uses the integral of the ionization rate along electric field lines calculated from the potential distribution. This allows the breakdown voltage to be estimated even from a poisson-only (or zero carrier) solution. The new algorithm allows users to choose the start positions of the electric field lines with more flexibility. This allows better results where the peak electric field is far removed from the device terminals. An example is the lateral DMOS device shown in Figure 5. The positions of the electric field lines used in the ionization integral calculation can now be saved to TonyPlot.

Improved analysis options

New PROBE command to allow solution quantities at a particular location within the device to be saved to the LOG file. PROBE can also record the max/min of given solution quantities
Improved plotting of vector solution variables such as electric field and current density. Previous versions would often show spikes or rough contours in areas of poor mesh
New averaging options on the OUTPUT statement can be used to select the best option for calculating electric field, current density and other quantities in the solution files
Plotting of depletion regions directly in TonyPlot
Normalized scale for current flowlines
When plotting an ATLAS solution file in TonyPlot, user can pres' b' on the keyboard to get a readout of terminal voltages and currents for the device

Several new features have been added to aid users in postprocessing analysis of their simulations. Most useful is the new PROBE statement. This allows users to select custom quantities to be saved in the LOG file. These quantities can then be plotted against the applied voltage, terminal currents or transient time. Quantities which can be saved are the values such as potential, electric field, lattice temperature, mobility or recombination rate at a given XY location. Also it is possible to select the minimum or maximum of a particular variable. Figure 6 shows a typical result that could be produced by the use of the PROBE statement. Multiple PROBE statements can be used to customize the contents of the LOG files.

New options on the OUTPUT statement have been added to reduce the amount of roughness in plots of vector quantities such as Electric field or current density from ATLAS.

Figure 5. TonyPlot visualization of electric field lines and depletion regions allow easier analysis of breakdown voltages using ionization integrals.

Figure 6. Using the PROBE statement users can select values to be stored into the log file. Here the potential at a point in the body of an SOI transistor is plotted versus drain bias. The large shift in potential corresponds with he kink in the IV curve.

Improved Handling of Bulk Traps

Trap distributions can now be specified using the DOPING statement. This allows use of all available types of distribution descriptions: uniform, gaussian, gaussian with lateral spread, ascii file and c-interpreter function
Improved visualization of trap density and occupancy
Allow specification of TRAP, INTTRAP and INTERFACE parameters by device in MixedMode simulations with multiple ATLAS-based devices

In power device applications, irradiation is used to tailor the minority carriers lifetime within the device structure. Traps are introduced into the structure with a spatial variation.[6] A new option to specify the TRAP density on the DOPING statement allows users to use the standard doping functions to describe this distribution. The options are 2D analytical functions, an ASCII file input or using the C-Interpreter to define the TRAP distribution. Enhancements have also been made in visualizing the trap occupancy. Figure 7 shows the occupancy of a trap level in a III-V device structure.

Improved High Frequency Analysis

AC simulations with distributed contact resistance allowed
Direct extraction of high frequency parameters into the LOG file: s-parameters, h-parameters, z parameters, y parameters, abcd parameters, stern stability factor, maximum transducer gain, maximum available gain

In previous versions of ATLAS a small set of high frequency parameters was available as postprocessing options using the UTMOST statement. Now direct extraction of high frequency AC parameters can be done using the LOG statement. This allows quantities from converged bias points tobe plotted before the simulation is completed. New parameters have also been added to the analysis including stern stability factor and maximum transducer gain.

Figure 7. Occupancy of the EL2 trap state in a MESFET. Plots of occupancy at each bias point allow analysis of trapping and detrapping effects.

Figure 8. S-parameter results from a high frequency MESFET.

Enhancements for Single Event Upset Simulation

C-Interpreter function F3.RADIATE to allow arbitrary functions in both position and time for charge generation
Allow UNIFORM generation rate
Instantaneous and Integrated Track charge are now saved to the LOG file

Modeling of radiation effects often requires the use of more complex radiation pulses than the previous ATLAS version would allow. By using the C-Interpreter users can now define arbitrary radiation pulses in both XYZ coordinates and time. Figure 9 shows a non-standard radiation pulse defined using the C-Interpreter.

Allow Mask experimentation in Interconnect3D

DELTA.CD parameters on ADDLAYER statement to allow feature size variations on a given mask layer
MISALIGN parameters on ADDLAYER statement to allow misalignment of layers for worst case parasitic extraction

In modern technologies it is a requirement to have some idea of the process variations for all aspects of the technology. Worst case and statistical modeling of transistors is a familiar concept. The same concept needs to be applied to interconnects as parasitics become more dominant in circuit performance issues. Modeling the nominal case for a given layout is simple in Interconnect3D, but the ability to apply process offsets in terms of CD variations and layer to layer misalignment must also be covered. New features in Interconnect3D allow users to simply specify line width variations and misalignments for a given layout file. Output from the simulator is in the form of SPICE netlists.

Figure 9. Photogeneration rate in Device3D from a function defined using the C-Interpreter.

Enhancements in 3D device simulation

Simulation with lumped resistors, capacitors and inductors allowed
Simulation with distributed contact resistance allowed.
Support for GaAs MESFETS
Added parameter to the SOLVE statement in Device3D to switch between the default ILUCGS iterative solver and the BICGST solver. The BICGST solve is enabled by setting the BICGST parameter of the SOLVE statement.

Figure 10. MESFET structure for 3D device simulation.

The 3D simulation products do benefit from many of the changes made to the 2D products. However there have been certain specific changes in Device3D. The ability to simulate with GaAs material parameters and models has been added. This allows users to simulate 3D MESFETs and GaAs diode structures. Device3D has also been enhanced to allow external elements to be attached to any contact. These elements are lumped resistance capacitance and inductance as well as distributed contact resistance. The new version also features a choice of iterative solvers the default is ILUCGS, however the faster, but less robust BICGST may could save CPU time for some case.

Non-linear current sources in MixedMode

Allows currents to be ramped up on a logarithmic scale

In many power device application sit is necessary to ramp the applied current up to a high value. Since convergence issues in ATLAS prevent applying large currents. Often it is inconvenient to do this with linear steps since ATLAS typically requires smaller steps at the start of a simulation run.

References

[1] Simulation Standard April 96, p1.

[2] Klaassen, D.B.M., "A Unified Mobility Model for Device Simulation - I. Model Equations and Concentration Dependence", Sol. St. Elec., V. 35,No. 7, pp. 953-959.

[3] Klaassen, D.B.M., "A Unified Mobility Model for Device Simulation - II. Temperature Dependence of Carrier Mobility and Lifetime", Sol. St.Elec., V. 35, No. 7, pp. 961-967.

[4] Shirahata M., Kusano H., Kotani N., Kusanoki S. and Akasaka Y., "A Mobility Model Including the Screening Effect in MOS Inversion Layer", IEEE Trans.Computer-Aided Design, V. 11, No. 9, pp. 1114-1119, Sep. 1992.

[5] Concannon, A., Piccinini, F., Mathewson, A., and Lombardi, C.,"The Numerical Simulation of Substrate and Gate Currents in MOS and EPROMs", IEDM95.

[6] P. Hazdra, J. Vobecky, Simulation Standard August 1995 p 2-3.