A SPAYN Analysis of Circuit Performance
Data Obtained Using the Virtual Wafer Fab

Introduction

In previous Simulation Standard articles it has been shown that UTMOST can be employed within the Virtual Wafer Fab (VWF) environment to extract circuit simulator device (SPICE) model parameter sets from data generated as a result of process and device simulations. UTMOST is used in batch mode, or more correctly in command-line mode, under DeckBuild to achieve this functionality. Now it is possible to run the SmartSpice circuit simulator under DeckBuild in the VWF framework. Command-line SmartSpice can be activated automatically during a VWF experiment and SmartSpice can also communicate successfully with a VWF database. This means that each of the process simulation, device simulation, parameter extraction, and circuit simulation tasks can be automatically accomplished during a VWF sensitivity, design-of-experiments, or Monte Carlo experiment. The details and logistics associated with the inclusion of SmartSpice simulations under VWF will be discussed in a future process and device simulation issue of the Simulation Standard. In this article we will describe a simple experiment which will demonstrate this new and extremely important VWF feature. The data which was produced in this VWF experiment will be analyzed here using SPAYN. Simple circuit performance macro models or behavioral models will be derived directly by SPAYN with the data provided by the VWF. Such macro models are valuable assets in situations where circuit design optimization or centering is required as they eliminate the need for time-consuming circuit simulations [2]. Circuit performance macro models using the actual process input variables as the predictors rather than SPICE model parameters are also very useful in process optimization or process centering applications. Costly process simulation and circuit simulation times can be vastly decreased using these macro models.

Experimental Description

The methodology by which so-called process corner SPICE models can be extracted using the VWF was described in a previous Simulation Standard article [1] entitled "Statistical Parameter Analysis for a Process Under Development Using SPAYN". This experiment involved the automated use of process simulation, device simulation, and parameter extraction tools. A Monte Carlo experiment was constructed in which process and mask parameters were allowed to vary randomly according to Gaussian distributions with specified means and standard deviations. Among the process and mask variables targeted for analysis were the P-well implant dose, the N-well implant dose, the gate oxidation pressure, the threshold voltage adjust implant dose, the polysilicon gate length, and the doping in the lightly doped N-type drain and source regions for a 0.6µm CMOS process. The main object of the experiment was to derive a system of equations which related the variations in certain process input parameters to variations in extracted SPICE BSIM3 parameters. This system of equations was derived using SPAYN. SPAYN was also used to construct the process corner models and to activate circuit simulations so that worst-case circuit performances could be identified. The circuit which was utilized was a simple CMOS inverter.

In this experiment the circuit simulations and the extraction of the circuit performance parameters were performed within the VWF rather than by SPAYN. Thus, the final VWF worksheet contained process input variables, device performance parameters (VTH, Beta, etc.), NMOS and PMOS BSIM3 model parameters, and circuit performance parameters. This data can be analyzed by the VWF, or exported to SPAYN for a more detailed analysis as we will do in this example. Circuit performance macro models were prepared using the Regression Analysis feature of SPAYN.

The circuit under analysis in this example was a simple CMOS inverter and the SmartSpice input file which was prepared for use in DeckBuild is shown in Figure 1. DeckBuild is Silvaco's interactive graphical run-time environment for the development of process simulation (ATHENA), device simulation (ATLAS), UTMOST command-line, and now SmartSpice command-line input decks. It consists of a window for input deck creation and editing, a window for product output control, and a set of popups for each product that provide full language and run-time support. Figure 2 shows a DeckBuild screen where the SmartSpice commands are loaded.

Figure 1. The SmartSpice commands used by DeckBuild for the analysis of the CMOS inverter.

Figure 2. The DeckBuild window showing some of the commands
related to the SmartSpice simulation under investigation.

The commands which appear in Figure 1 consist of the initialization command for SmartSpice (go SmartSpice), the .option and netlist statements for the CMOS inverter, the .dc and .save SmartSpice statements, the circuit .measure statements, the NMOS and PMOS model cards, and the DeckBuild solve and extract commands enabling the measured circuit performances to be stored in the VWF. The SmartSpice .measure statements are configured to measure the inverter trip (trigger) voltage, trip current, and small-signal gain. The .model statements make references to BSIM3 NMOS and PMOS parameters previously extracted by command-line UTMOST, and stored in the VWF database, for the process "split" in question. Almost 100 process splits were performed in this experiment.

Analysis of Results Using SPAYN

The process, SPICE model, and circuit performance parameters were imported into SPAYN. Histograms of the extracted device performances appear in Figure 3. An analysis of the entire parametric correlation matrix proved that while the inverter trip voltage and current were highly correlated to certain SPICE parameters, the correlations with the process parameters were significantly weaker. The inverter gain was not strongly correlated to any one process or SPICE parameter. Figure 4 shows some scatter plots showing the relationships between the inverter trip voltage and current to some important SPICE BSIM3 parameters.

Figure 3. Histograms of the extracted CMOS inverter circuit parameters.

Figure 4. Selected scatter plots showing the extracted CMOS inverter
performance parameters and some SPICE parameters.

A PCA analysis of the parametric data exposed the PMOS K1, the NMOS UO,the PMOS VTH0, and the PMOS VSAT parameters as being the important independent or dominant BSIM3 parameters. This importance is based on the amount of the variability of the other NMOS and PMOS model parameters which can be predicted as a function of these dominant parameters. Attempts were then made to derive so-called macro models for the circuit performances under analysis using the SPAYN Regression facility and the dominant SPICE parameters derived i.e.

Circuit Performance = Z = F( K1_P, UO_N, VTH0_P, VSAT_P )

Table 1 shows the R-squared (R2) values associated with fitting models of varying degrees of complexity to the inverter circuit characteristics. The predictor variables were the four dominant parameters identified above. Also tabulated are the average percentage errors associated with the derived estimates for the circuit parameters.

Table 1. Regression model information where four dominant SPICE parameters are used.

Figure 5 shows scatter plots of the macro model estimates of the three circuit performances versus the actual circuit performances. In these plots the regression model includes all terms up to and including the cubic terms. The prediction of the trip voltages and currents are adequate but the prediction of the small-signal gain is not so good with an R2 value of less than 0.5. This was probably due to the need for extra parameters in the dominant parameter predictor set, particularly those affecting the determination of device output conductance (gds) and transconductance (gm). The small-signal CMOS inverter gain is very dependent on these device conductances.

Figure 5. Scatter plots of modeled (SPICE parameter regression model)
and actual (SmartSpice simulations) circuit performance parameters.

The process quantities which were varied as part of the VWF experiment were also stored in the SPAYN database. These variables were the pwell_dose, nwell_dose, gateox_press, vtadj_dose, poly_cd, and NLDD_dose parameters. It was decided to create circuit macro models in terms of these quantities also i.e.

	Circuit Performance = Z = F
		(( pwell_dose, nwell_dose, 	
			gateox_press, vtadj_dose,
			poly_cd, NLDD_dose )

Table 2 shows the R-squared (R2) values associated with fitting models of varying degrees of complexity to the inverter circuit characteristics. The predictor variables were the six process parameters mentioned above. Also tabulated are the average percentage errors associated with the derived estimates for the circuit parameters.

Table 2. Regression model information where six process parameters are used.

Figure 6 shows scatter plots of the process parameter based macromodel estimates for the three circuit performances versus the actual circuit performances. In these plots the regression model includes all terms up to and including the cubic terms. The prediction of the trip voltages and currents are adequate, even in the case of the simple linear models with no interaction terms. The prediction of the small-signal gain requires the full cubic model in order to achieve the required accuracy. In this example the process parameter regression models using six predictors were more accurate than the SPICE parameter regression models employing only four terms.

Figure 6. Scatter plots of modeled (process parameter regression model)
and actual (SmartSpice simulations) circuit performance parameters.

Conclusions

It is now possible to perform SmartSpice circuit simulations, and extract circuit performance parameters, during a VWF experiment. Using this new capability a SPAYN database consisting of process, SPICE model, and circuit performance parameters was constructed. SPAYN was then used to prepare two different sets of macro models or behavioral models for a simple CMOS circuit. The two model sets differed in the choice of the predictor variables. The first used a subset of the SPICE model parameters and the second used the process variables which were varied during the initial VWF experiment. Use was made of the SPAYN PCA facility to identify the independent subset of dominate SPICE model parameters, while the SPAYN regression facility was used to construct and evaluate the macro models. Using such circuit performance macro models in place of multiple circuit simulations drastically reduces analysis times during circuit performance optimization or circuit performance centering experiments. These macro models are also beneficial in more wide-ranging process optimization or process centering applications where they serve to reduce the amount of process simulation, device simulation, and circuit simulations required.

References

1. Simulation Standard, Vol.6, Number 5, May 1995.
2. T-K Yu et al., "Statistical Performance Modeling and Parametric Yield Estimation of MOS VLSI," IEEE Transactions on Computer-Aided Design, Vol. CAD-6, No.6, Nov. 1987.