Interconnect Simulation

The full text for most of these papers may be found at the IEEE website at www.ieee.org.

Keh-Jeng Chang, Jyh-Jeng Chou, Hung-Chih Li, and Kuo-Cheng Chang
"Impact quantification of the dummy metal fills on nanometer VLSI designs for DFM",
International Symposium on VLSI Design, Automation and Test, 2008. VLSI- DAT 2008. IEEE, April 2008, pp. 291 - 294

A.K. Goel, and H. Gopinathannair
"Capacitance extraction for the nanoscale on-chip interconnects"
IEEE International Conference on Semiconductor Electronics, Dec 2004, pp. 112- 116.

B. Froment, E. Guichard, B. Borot, S. Hanriat, J. Cluzel, J.-P.
Schoellkopf, and H. Jaouen
"New interconnect capacitance characterization method for multilevel metal CMOS processes"
IEEE International Conference on Interconnect Technology, 1999, pp. 224 - 226

S. Putot, F. Charlet, and P. Witomski
"A fast and accurate computation of interconnect capacitance"
International Electron Device Meeting, Dec. 1999, pp. 893-896