Finfet

The full text most of these papers may be found at the IEEE website at www.ieee.org.

A. Kranti et al.,
"Comparative analysis of nanoscale MOS device architectures for RF applications",
Semiconductor Science and Technology, vol. 22, no. 5, pp. 481-491, 2007.

A. Kranti et al.,
"Significance of gate underlap architecture in FinFETs for low–voltage analog/rf applications", 211th Electrochemical Society Meeting (Chicago, USA), In Proc. ECS Transactions (SOI Device Technology), vol. 6, no. 4, pp. 375-380, 2007.

A. Kranti et al.,
"Comparative analysis of nanoscale MOS device architectures for RF applications",
Semiconductor Science and Technology, vol. 22, no. 5, pp. 481-491, 2007.

A. Kranti et al.,
"Device design considerations for nanoscale double and triple gate FinFETs", In Proc. 2005 IEEE SOI Conference, Honolulu, Hawaii, USA, pp. 96-98, 2005.

Byung-Kil Choi, Kyoung-Rok Han, Young Min Kim, Young June Park, Jong-Ho Lee "Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs) Electron Devices"
IEEE Transactions on Vol. 54, Issue 3, March 2007 pp. 537 - 545