A. A. Salman, R. Gauthier, C. Putnam, P. Riess, M. Muhammad, M. Woo, D. E. Ioannou
"ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-"
IEEE Transactions on Device and Materials Reliability, Vol. 3, Issue 3, September 2003, pp. 79

J. A. Salcedo, J. J. Liou, J. C. Bernier
"Design and integration of novel SCR-based devices for ESD protection in CMOS/BiCMOS technologies"
IEEE Transactions on Electron Devices, Vol. 52, Issue 12, December 2005, pp. 2682-2689

Z. Zhu, Y. Hao
"Characterization simulation of a deep sub-micron GGNMOSFET under TLP stress"
Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, Vol. 26, Issue 10, October 2005, pp. 196

J.-Y. Choi
"AC modeling of the ggNMOS ESD protection device"
ETRI Journal, Vol. 27, Issue 5, October 2005, pp. 628-634

J. -Y. Choi, W. S. Yang, D. Kim, Y. Kim
"Thyristor input-protection device suitable for CMOS RF IC's"
Analog Integrated Circuits and Signal Processing, Vol. 43, Issue 1, April 2005, pp. 5-14

X. Gao, J. J. Liou, W. Wong, S. Vishwanathan
"An improved electrostatic discharge protection structure for reducing triggering voltage and parasitic capacitance"
Solid-State Electronics, Vol. 47, June 2003, pp. 1105-1110

X. Gao, J. J. Liou, J. Bernier, G. Croft, W. Wong, S. Vishwanathan
"Optimization of on-chip ESD protection structures for minimal parasitic capacitance"
Microelectronics Reliability, Vol. 43, May 2003, pp. 725-733

A. Guilhaume, P. Galy, J. P. Chante, B. Foucher, S. Bardy, F. Blanc
"ESD evaluation of a low voltage triggering SCR (LVTSCR) device submitted to transmission line pulse (TLP) test"
Journal of Electrostatics, Vol. 56, October 2002, pp. 281-294

Gianluca Boselli, Stan Meeuwsen, Ton Mouthaan and Fred Kuper,
"Investigations on double-diffused MOS transistors under ESD zap conditions"
Microelectronics Reliability, Vol. 41, Issue 3, March 2001, pp. 395-405

J. J. Liou and X. Gao
"Design and modeling of on-chip electrostatic discharge (ESD) protection structures"
Proceedings of the International Conference on Microelectronics, Vol. 24 II, 2004, pp. 619-624

A. Salman, R. Gauthier, E. Wu, P. Riess, C. Putnam, M. Muhammad, M. Woo, D. Ioannou
"Electrostatic discharge induced oxide breakdown characterization in a 0.1"
Annual Proceedings - Reliability Physics (Symposium), 2002, pp. 170-174

A. Guilhaume et al
"Simulation and experimental comparison of GGNMOS and LVTSCR protection cells under ElectroStatic Discharges"
ESREF2001, pp. 1433-1437

J. C. Lee, A. Hoque, G. D. Croft, J. J. Liou, R. Young and J. C. Bernier
"An electrostatic discharge failure mechanism in semiconductor devices, with applications to electrostatic discharge measurements using transmission line pulsing technique"
Solid-State Electronics, Vol. 44, Issue 10, 1 October 2000, pp. 1771-1781

Kevin Palser, Ann Concannon, Ray Duffy and Alan Mathewson,
"Analysis of external latch-up protection test structure design using numerical simulation"
Microelectronics and Reliability, Vol. 39, Issue 5, May 1999, pp. 647-659

Kyuhyung Kwon et al
"A Novel ESD Protection Technique for Submicron CMOS/BiCMOS Technologies"
Proc. EOS/ESD Symposium, 1995, pp. 21-26

Freydin, Strachan
"Simulation of Electrothermal Interactions in ESD Protection Devices"
In-house paper, 1994

Hellstrom, Freydin, Velmre, Uda
"Numerical Simulation of Electrothermal Effects in ESD Protection Devices"
ESREF, 1992

Freydin, Velmre, Udal
"Numerical Simulation of Electrothermal Interactions in Semiconductor Devices Experiencing ESD Pulses"
Pro. Int Workshop on Computational Electronics