CMOS Technology

The full text for most of these papers may be found at the IEEE website at www.ieee.org.

Ravneet Kaur, Rishu Chaujar, Manoj Saxena, R.S. Gupta,
"Two dimensional simulation and analytical modeling of a novel ISE MOSFET with gate stack configuration",
Microelectronic Engineering, Vol. 86, Issue 10, October 2009, pp. 2005-2014

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta, R.S. Gupta,
"TCAD assessment of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET and its multi-layered gate architecture, Part II: Analog and large signal performance evaluation",
Superlattices and Microstructures, Vol. 46, Issue 4, October 2009, pp. 645-655

Xi Liu, Xiaoshi Jin, Jong-Ho Lee,
"A compact model of fringing field induced parasitic capacitance for deep sub-micrometer MOSFETs",
Solid-State Electronics, Vol. 53, Issue 9, September 2009, pp. 1041-1045

B. Ayub, M. Rusop,
"The effect of gate dielectric thickness on PMOS performance",
AIP Conference Proceedings, Vol. 1136, 2009, pp. 560-564

O. Suziana, B. Ayub, M. Redzuan, A. R. Shahrir, M. Y. Yunus, M. H. Abdullah, U. M. Noor, M. Rusop,
"Effect of doping concentration on electrical characteristics of NMOS structure",
AIP Conference Proceedings, Vol. 1136, 2009, pp. 575-580

M. Redzuan, B. Ayub, M. Shahrir, O. Suziana, M. Yunus, M. H. Abdullah, U. M. Noor, M. Rusop,
"Mesh grid of SILVACO TCAD effect on net doping profile for NMOS structures",
AIP Conference Proceedings, Vol. 1136, 2009, pp. 581-585

A. R. Shahrir, M. Rusop,
"The threshold voltage properties of NMOS structure etched with different etching methods",
AIP Conference Proceedings, Vol. 1136, 2009, pp. 555-559

S. F. W. M. Hatta, N. Soin,
"Design of a low voltage CMOS LNA at 2 GHz with substrate-bias",
AIP Conference Proceedings, Vol. 1060, 2008, pp. 244-249

K. Romanjek, E. Augendre, W. Van Den Daele, B. Grandchamp, L. Sanchez, C. Le Royer, J.-M. Hartmann, B. Ghyselen, E. Guiot, K. Bourdelle, S. Cristoloveanu, F. Boulanger, L. Clavelier,
"Improved GeOI substrates for pMOSFET off-state leakage control Microelectronic Engineering",
In Press, Corrected Proof, Available online 16 March 2009.

Ravneet Kaur, Rishu Chaujar, Manoj Saxena, R. S. Gupta,
"Two dimensional simulation and analytical modeling of a novel ISE MOSFET with gate stack configuration",
Microelectronic Engineering, In Press, Corrected Proof, Available online 17 January 2009.

P. Martin, M. Cavelier, R. Fascio, G. Ghibaudo, M. Bucher,
"EKV3 compact modeling of MOS transistors from a 0.18 μm CMOS technology for mixed analog–digital circuit design at low temperature Cryogenics",
In Press, Corrected Proof, Available online 1 January 2009.

Lizhe Tan, Octavian Buiu, Stephen Hall, Enrico Gili, Takashi Uchino, Peter Ashburn,
"The influence of junction depth on short channel effects in vertical sidewall MOSFETs",
Solid-State Electronics, Vol. 52, Issue 7, July 2008, pp. 1002-1007.

F. Lime, B. Iniguez, O. Moldovan,
"A quasi-two-dimensional compact drain-current model for undoped symmetric double-gate MOSFETs including short-channel effects",
IEEE Transactions on Electron Devices, Vol. 55, No. 6, June 2008, pg. 1441-1448.

Yu. P. Snitovsky, M. G. Krasikov,
"New CMOS process using a thermal-oxide mask for making n- - and p- - wells", Russian Microelectronics, Vol. 37, No. 3, May 2008, pp. 166-174.

A. S. Zoolfakar, H. Hashim,
"Comparison between Experiment and Process Simulation Results for Converting Enhancement to Depletion Mode NMOS Transistor",
Second Asia International Conference on Modeling & Simulation,
2008. AICMS 08. 13-15 May 2008 pp. 1061 - 1064.

M. Elgin, D. Russell, M. Katula, R. Paulsen, S. Parke,
"CMOS imager pixel design for space applications",
Microelectronics and Electron Devices, 2006. WMED '06. 2006 IEEE Workshop on 14 April 2006, pp. 1.

F. Mayer, C. Le Royer, G. Le Carval, C. Tabone, L. Clavelier and S. Deleonibus,
"Comparative study of the fabricated and simulated Impact Ionization MOS (IMOS)",
Solid-State Electronics, Vol. 51, Issue 4, April 2007, pp. 579-584.

X. Loussier, D. Munteanu and J.L. Autran, "Impact of high-permittivity dielectrics on speed performances and power consumption in double-gate-based CMOS circuits",
Journal of Non-Crystalline Solids, Vol. 353, Issues 5-7, 1 April 2007, pp. 639-644.

Jong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park, "Design and simulation of asymmetric MOSFETs ",
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E90-C, No. 5, May 2007, p 978-982.

Ulrich Abelein, Andreas Assmuth, Peter Iskra, Markus Schindler, Torsten Sulima and Ignaz Eisele, "Doping profile dependence of the vertical impact ionization MOSFET´s (I-MOS) performance",
Solid-State Electronics, Vol. 51, Issue 10, October 2007, pp. 1405-1411.

Jong Pil Kim (Seoul Nat. Univ., Seoul, South Korea); Woo Young Choi; Jae Young Song; Sang Wan Kim; Jong Duk Lee; Byung-Gook Park, "Design and fabrication of asymmetric MOSFETs using a novel self-aligned structure",
IEEE Transactions on Electron Devices, Vol. 54, No. 11, Nov. 2007, p 2969-2974.

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta,
"Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI",
Microelectronic Engineering, Vol. 85, Issue 3, March 2008, pp. 566-576.

Rishu Chaujar, Ravneet Kaur, Manoj Saxena, Mridula Gupta and R.S. Gupta,
"Laterally amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET for ULSI",
Microelectronic Engineering, Vol. 85, Issue 3, March 2008, pp. 566-576.

G. Pei, E. C. -C. Kan
"Independently driven DG MOSFETs for mixed-signal circuits: Part I - Quasi-static and nonquasi-static channel coupling"
IEEE Transactions on Electron Devices, Vol. 51, Issue 12, December 2004, pp. 2086-2093

G. Pei, E. C. C. Kan
"Independently driven DG MOSFETs for mixed-signal circuits: Part II - Applications on cross-coupled feedback and harmonics generation"
IEEE Transactions on Electron Devices, Vol. 51, Issue 12, December 2004, pp. 2094-2101

M. Masahara, Y. Liu, S. Hosokawa, T. Matsukawa, K. Ishii, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, E. Suzuki
"Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching"
IEEE Transactions on Electron Devices, Vol. 51, Issue 12, December 2004, pp. 2078-2085

A. Mannargudi, D. Vasileska
"Quantum confinements in highly asymmetric sub-micrometer device structures"
Superlattices and Microstructures, Vol. 34 (3-6), Sep-Dec 2003, pp. 347-354

B. Villard, F. Calmon, C. Gontrand
"Design and characterization of high voltage devices integrated in a standard CMOS technology"
EPJ Applied Physics, Vol. 16, Issue 2, November 2001, pp. 113-120

N. G. Gunther, I. I. Pesic, A. A. Mutlu, M. Rahman
"Modeling C - V characteristics of deep sub-0.1 micron mesoscale MOS devices"
Solid-State Electronics, Vol. 48, Issue 10-11 SPEC. ISS., October 2004, pp. 1883-1890

G. M. Laws, T. J. Thornton, J. Yang, L. De La Garza, M. Kozicki, D. Gust
"Molecular control of the drain current in a buried channel MOSFET"
Physica Status Solidi (B) Basic Research, Vol. 233, Issue 1, September 2002, pp. 83-89

N. D. Jankovic and G. A. Armstrong
"Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers"
Microelectronics Journal, Vol. 35, Issue 8, August 2004, pp. 647-653

F. -L. Chang, M. -J. Lin, C. W. Liaw, T. -C. Liao, H. -C. Cheng
"Investigation of A 450 V rating silicon-on-insulator lateral-double-diffused-metal-oxide-semiconductor fabrication by 12/25/5/40 V bipolar-complementary metal-oxide-semiconductor double-diffused metal-oxide-semiconductor process on bulk silicon substrate"
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol.u

A. R. Saha, S. Chattopadhyay, C. Bose, C. K. Maiti
"Technology CAD of silicided Schottky barrier MOSFET for elevated source-drain engineering"
Materials Science and Engineering B: Solid-State Materials for Advanced Technology, Vol. 124-125

K. Chong, X. Zhang, K.-N. Tu, D. Huang, M.-C. Chang, Y.-H. Xie
"Three-dimensional substrate impedance engineering based on p-/p+ Si substrate for mixed-signal system-on-chip (SoC)"
IEEE Transactions on Electron Devices, Vol. 52, Issue 11, November 2005, pp. 2440-2446

P. Kasturi, M. Saxena, R. S. Gupta
"Modeling and simulation of STacked Gate Oxide (STGO) architecture in Silicon-On-Nothing (SON) MOSFET"
Solid-State Electronics, Vol. 49, Issue 10, October 2005, pp. 1639-1648

M. De Souza, M. A. Pavanello, B. Iniguez, D. Flandre
"A charge-based continuous model for submicron graded-channel nMOSFET for analog circuit simulation"
Solid-State Electronics, Vol. 49, Issue 10, October 2005, pp. 1683-1692

G. Nicholas, T. J. Grasby, E. H. C. Parker, T. E. Whall, T. Skotnicki
"Evidence of reduced self-heating in strained Si MOSFETs"
IEEE Electron Device Letters, Vol. 26, Issue 9, September 2005, pp. 684-686

M. Masahara, Y. Liu, K. Sakamoto, K. Endo, T. Matsukawa, K. Ishii, T. Sekigawa, H. Yamauchi, H. Tanoue, S. Kanemaru, H. Koike, E. Suzuki
"Demonstration, analysis, and device design considerations for independent DG MOSFETs"
IEEE Transactions on Electron Devices, Vol. 52, Issue 9, September 2005, pp. 2046-2053

G. Curatola, G. Doornbos, J. Loo, Y. V. Ponomarev, G. Iannaccone
"Detailed modeling of sub- 100-nm MOSFETs based on Schrodinger DD per subband and experiments and evaluation of the performance gap to ballistic transport"
IEEE Transactions on Electron Devices, Vol. 52, Issue 8, August 2005, pp. 1851-1858

D. Munteanu, J. L. Autran, S. Harrison
"Quantum short-channel compact model for the threshold voltage in double-gate MOSFETs with high-permittivitty gate dielectrics"
Journal of Non-Crystalline Solids, Vol. 351, Issue 21-23, 15 July 2005, pp. 1911-1918

V. D'Alessandro, P. Spirito
"Achieving accuracy in modeling the temperature coefficient of threshold voltage in MOS transistors with uniform and horizontally nonuniform channel doping"
Solid-State Electronics, Vol. 49, Issue 7, July 2005, pp. 1098-1106

S. C. Kelly, J. A. Power, M. O'Neill
"Selection and modeling of integrated RF varactors on a 0.35-"
IEEE Transactions on Semiconductor Manufacturing, Vol. 17, No. 2, May, 2004, The International Co

G. Z. Zheng, Y. J. Luo, W. Q. Yang, S. Y. Zhou, Z. Jiang, X. F. Zong
"Calculation, experience and simulation of hot-carrier effect in MOSFET's"
Guti Dianzixue Yanjiu Yu Jinzhan/Research & Progress of Solid State Electronics, Vol. 21, Issue 2

J. Yuan, J. C. S. Woo
"A novel split-gate MOSFET design realized by a fully silicided gate process for the improvement of transconductance and output"
IEEE Electron Device Letters, Vol. 26, Issue 11, November 2005, pp. 829-831

T. -S. Park, E. Yoon, J. -H. Lee
"A 40 nm body-tied FinFET (OMEGA MOSFET) using bulk Si wafer"
Physica E: Low-dimensional Systems and Nanostructures, Vol. 19, Jul. 2003, pp. 6 -12

R. Granzner, V. M. Polyakov, F. Schwierz, M. Kittler, T. Doll
"On the suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs"
Physica E: Low-dimensional Systems and Nanostructures, Vol. 19, Jul. 2003, pp. 33 - 38

E. J. Preisler, S. Guha, B. R. Perkins, D. Kazazis, A., Zaslavsky
"Ultrathin epitaxial germanium on crystalline oxide metal-oxide-semiconductor-field-effect transistors"
Applied Physics Letters, Vol. 86, Issue 22, 2005, pp. 1-3

M. Masahara, Y. Liu, S. Hosokawa, T. Matsukawam K. Ishii, H. Tanoue, K. Sakomoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, and E. Suzuki
"Ultrathin Channel Vertical DG MOSFET Fabricated by using Ion-Bombardment-Retarded Etching"
IEEE Trans, Electron Devices, Vol. 51, Dec 2004, pp. 2078-2085

Pascal Scheiblin and Johann Foucher
"Three-Dimensional Simulation of the Effect of E-Beam Lithography Induced Line-Edge Roughness on N-Type Metal-Oxide Semiconductor Transistor Electrical Characteristics for a 50nm Technology"
Japanese Journal of Applied Physics Vol. 43 No. 6B, 2004, pp. 3838-3842

J. Yuan and J. C. S. Woo
"Nanoscale MOSFET with split-gate design for RF/analog application"
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers, Vol.
43, No. 4B, pp. 1742-1745(2004)

E. Gili, V. D. Kunz, C. H. De Groot, T. Uchino, P. Ashburn, D. C. Donaghy, S. Hall, Y. Wang, P. L. F. Hemment
"Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance"
Solid-State Electronics, Vol. 48, Issue 4, April 2004, pp. 511-519

Iliya Pesic, Norman Gunther, Ayhan Mutlu, and Mahmud Rahman
"Modeling C-V Characterisitics of Deep Sub - 0.1 Micron Mesoscale MOS Devices"
Proceedings of 2003 International Semiconductor Device Research Symposium, Washington DC, December 1

A. Breed and K. P. Roenker
"Dual-gate (FinFET) and Tri-Gate MOSFETs: Simulation and Design"
Proceedings of 2003 International Semiconductor Device Research Symposium, Washington DC, December 1

M. Saxena, S. Haldar, M. Gupta, R. S. Gupta
"Modeling and simulation of asymmetric gate stack (ASYMGAS)-MOSFET"
Solid-State Electronics, Vol. 47, November 2003, pp. 2131-2134

T. Ivanov, T. Gotszalk, T. Sulzbach, I. W. Rangelow
"Quantum size aspects of the piezoresistive effect in ultra thin piezoresistors"
Ultramicroscopy, Vol. 97, October-November 2003, pp. 377-384

M. Masahara, T. Matsukawa, H. Tanoue and et al.,
"Novel process for vertical double-gate (DG) metal-oxide-semiconductor field-effect-transistor (MOSFET) fabrication"
Jpn. J. Appl. Phys. 1, Vol. 42, Jun. 2003, pp. 4138 - 4141

G. M. Laws, T. J. Thornton, J. Yanga, L. de la Garza, M. Kozicki, D. Gust, J. Gu, D. Sorid
"Drain current control in a hybrid molecular/MOSFET device"
Physica E: Low-dimensional Systems and Nanostructures, Vol. 17, April 2003, pp. 659 - 663

M. Masahara, T. Matsukawa, K. Ishii and et al.,
"Fabrication of ultrathin Si channel wall for vertical double-gate metal-oxide-semiconductor field-effect transistor (DG MOSFET) by using ion-bombardment-retarded etching (IBRE)"
Jpn. J. Appl. Phys. 1, Vol. 42, Apr. 2003, pp. 1916 - 1918

T. Ivanov, T. Gotszalk, T. Sulzbach, I. Chakarov and I. W. Rangelow
"AFM cantilever with ultra-thin transistor-channel piezoresistor: quantum confinement"
Microelectronic Engineering, Vol. 67-68, 2003, pp. 534-541

H. Koo, K. Lee, K. Lee, T. A. Fjeldly, M. S. Shur
"Analysis of the anomalous drain current characteristics of halo MOSFETs"
Solid-State Electronics, Vol. 47, January 2003, pp. 99-106

Anand Mannargudi and Dragica Vasileska
"Monte Carlo and Energy Balance Simulations of Deep-micrometer Conventional and Asymmetric MOSFET Device Structures"
Nanotech 2003, Vol. 2, pp. 1-4

M. Saxena, S. Haldar, M. Gupta and et al.,
"Physics-based modelling and simulation of dual material gate stack (DUMGAS) MOSFET"
Electron Letter, Vol. 39, Jan. 2003, pp. 155-157

F. Pregaldiny, C. Lallement, D. Mathiot
"A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs"
Solid-State Electronics, Vol. 46, December 2002, pp. 2191-2198

S. Persson, P. -E. Hellberg and S. -L. Zhang
"A charge sheet model for MOSFETs with an abrupt retrograde channel: Part II. Charges and intrinsic capacitances"
Solid-State Electronics, Vol. 46, Issue 12, Dec. 2002, pp. 2217-2225

M. Saxena, S. Haldar and M. Gupta, et al.,
"Physics-based analytical modeling of potential and electrical field distribution in dual material gate (DMG)-MOSFET for improved hot electron effect and carrier transport efficiency"
IEEE Trans. Electron Devices, Vol. 49, Nov. 2002, pp. 1928-1938

Fernando Gonz?z, Sr. , Suraj J. Mathew and J. Alex Chediak
"A dynamic source-drain extension MOSFET using a separately biased conductive spacer"
Solid-State Electronics, Vol. 46, Issue 10, Oct. 2002, pp. 1525-1530.

X. Gao, J. J. Liou, J. Bernier and G. Croft
"An improved model for substrate current of submicron MOSFETs"
Solid-State Electronics, Vol. 46, Issue 9, Sep. 2002, pp. 1395-1398

L. Vestling, J. Olsson and K. -H. Eklund
"Drift region optimization of lateral RESURF devices"
Solid-State Electronics, Vol. 46, Issue 8, Aug. 2002, pp. 1177-1184

D. Munteanu, G. Le Carval and G. Guegan
"Impact of technological parameters on non-stationary transport in realistic 50 nm MOSFET technology"
Solid-State Electronics, Vol. 46, Issue 7, Jul. 2002, pp. 1045-1050

A. Gokirmak, S. Tiwari
"Threshold voltage tuning and suppression of edge effects in narrow channel MOSFETs using surrounding buried side-gate"
Electronics Letters, Vol. 41, Issue 3, 3 February 2005, pp. 157-158

Seong-Dong Kim, et al.
"Advanced model and analysis of series resistance for CMOS scaling into nanometer regime - part 1: theoretical derivation"
IEEE Trans. Electron Devices, vol.49, No.3, March 2002, pp.457 - 466

C. Caillat, S. Deleonibus, G. Guegan, M. Heitzmann, M. E. Nier, S. Tedesco, B. Dal'zotto, F. Martin, P. Mur, A. M. Papon et al.
"A 20 nm physical gate length NMOSFET with a 1.2 nm gate oxide fabricated by mixed dry and wet hard mask etching"
Solid-State Electronics, Vol. 46, Issue 3, March 2002, pp. 349-352

Juin J. Liou, R. Shireen, A. Ortiz-Conde, F. J. Garcia Sanchez, A. Cerdeira, X. Gao, Xuecheng Zou and C. S. Ho
"Influence of polysilicon-gate depletion on the subthreshold behavior of submicron MOSFETs"
Microelectronics Reliability, Vol. 42, Issue 3, March 2002, pp. 343-347

Yee-Chia Yeo, Subramanian V. Kedzierski J., Peiqi Xuan, Tsu-Jae King, Bokor J., Chenming Hu,
"Design and Fabrication of 50-nm Thin-Body p-MOSFETs With a SiGe Heterostructure Channel"
IEEE Trans. Electron Devices, Vol. 49, Feb. 2002, pp. 279 - 286.

I. Nam, K. Lee
"High-performance RF mixer and operational amplifier BiCMOS circuits using parasitic vertical bipolar transistor in CMOS technology"
IEEE Journal of Solid-State Circuits, Vol. 40, Issue 2, February 2005, pp. 392-402

L. Mao, H. Nian, P. Gao, S. Zhang, W. Guo, S. Zhang
"Mixed-mode circuit and device simulation for an optoelectronic integrated receiver"
Proceedings of SPIE - The International Society for Optical Engineering, Vol. 4919, 2002, pp. 507

S. Persson, P. -E. Hellberg and S. -L. Zhang
"A charge sheet model for MOSFETs with an abrupt retrograde channel: Part I. Drain current and body charge"
Solid-State Electronics, Vol. 46, Issue 12, Dec. 2002, pp. 2209-2216

Milne, PR
"Design, Simulation, and Fabrication of a BiCMOS VLSI Digitally Programmable GIC Filter"
Naval Postgraduate School, Monterey, CA. Sep 2001. 97p. NTIS ADA397177

G. Kamoulakos, Y. Tsiatouhas, A. Chrisanthopoulos and et al.,
"A high-density DRAM cell with built-in gain stage"
IEEE Trans. Electron Devices, Vol. 48, Jun. 2001, pp. 1194 - 1199

A. Ohata,
"Evaluation of performance degradation factors for high-k gate dielectrics in N-channel MOSFETs"
Solid-State Electronics, Vol. 48, Feb. 2004, pp. 345 - 349

K. Goel, M. Saxena, M. Gupta, R. S. Gupta
"Two-dimensional analytical threshold voltage model for DMG Epi-MOSFET"
IEEE Transactions on Electron Devices, Vol. 52, Issue 1, January 2005, pp. 23-29

S. -E. Tan
"Velocity saturation in PMOSFET: Using different inversion layer mobility models"
10th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2004: Integrated Sys

S. -E. Tan
"Effects of normal electric field on submicrometer PMOSFET"
10th International Symposium on Integrated Circuits, Devices and Systems, ISIC-2004: Integrated Sys

Y. David and U. Efron
"Design and analysis of an image transceiver device with a low cross-talk level"
IEEE Convention of Electrical and Electronics Engineers in Israel, Proceedings 2004, pp. 41-43

T. Uchino, P. Ashburn, Y. Kiyota, T. Shiba
"A CMOS-compatible rapid vapor-phase doping process for CMOS scaling"
IEEE Transactions on Electron Devices, Vol. 51, Issue 1, January 2004, pp. 14-19

H. Lee, H. Shin, J. Lee
"Design of a 20 nm T-gate MOSFET with a Source/Drain-to-Gate Non-Overlapped Structure"
Journal of the Korean Physical Society, Vol. 44, Issue 1, January 2004, pp. 65-68

M. -A. Jaud, S. Barraud, G. Le Carval
"Impact of quantum mechanical tunneling on off-leakage current in double-gate MOSFET using a quantum drift-diffusion model"
2004 NSTI Nanotechnology Conference and Trade Show - NSTI Nanotech 2004 Vol. 2, 2004, pp. 17-20

M. Masahara, T. Matsukawa, K. -I. Ishii, Y. Liu, H. Tanoue, K. Sakamoto, T. Sekigawa, H. Yamauchi, S. Kanemaru, E. Suzuki
"15-nm-thick Si channel wall vertical double-gate MOSFET"
Technical Digest - International Electron Devices Meeting, 2002, pp. 949-951.

D. Munteanu, G. Le Carval, G. Guegan
"Impact of non-stationary transport effects on realistic 50nm MOS technology"
2001 International Conference on Modeling and Simulation of Microsystems - MSM 2001, 2001, pp. 46

N. Takaura, R. Nagai, H. Asakura, S. Yamada, S. Kimura
"A new method for analyzing boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design"
IEEE International Conference on Microelectronic Test Structures, 2001, pp. 171-176

J. Kang, X. He, D. Vasileska and D. K. Schroder
"Optimization of FIBMOS through 2D Silvaco ATLAS and 2D Monte Carlo particle-based device simulations"
VLSI Design, Vol. 13, No. 1-4, 2001, pp. 251-256

F. Duvivier, E. Guichard
"Worst-case SPICE model generation for a process in development using ATHENA, ATLAS, UTMOST and SPAYN"
The 13th IEEE International Conference on Microelectronics (ICM 2001), pp. 11 -18

W. Zagozdzon-Wosik, L. Shao, M. Menon, E. Arroyo-Castelazo, I. Rusakova, X. Wang, P. van der Heide, J. Liu, W. K. Chu and J. Bennet
"Device and material issues related to integration of junctions with contacts in deep 0.1 /spl mu/m MOSFETs"
Advanced Thermal Processing of Semiconductors 9th IEEE International Conference on RTP 2001, pp. 82

Allibert F. Zaslavsky A. Pretet J. Cristoloveanu S.
"Double-Gate MOSFETS : Is Gate alignment Mandatory?"
Proc. ESSDERC 2001

Schwantes S. Krautschneider W.
"Relevance of Gate Current for the Functionnality of Deep Submicron CMOS Circuits"
Proc. ESSDERC 2001

Landgraf E. Rosner W. Luyken R.J.
"High On Current in Quasi Double Gate Transistors with Undoped Channel Region"
Proc. ESSDERC 2001

D. Y. Chung and J. H. Lee,
"Design consideration of self-aligned recessed channel (RC) devices in sub-100 nm CMOS technology"
Journal Korean Phys. Soc., Vol. 37, Nov. 2000, pp. 617 - 623

C. W. Liu and T. X. Hsieh
"Analytic modeling of the subthreshold behavior in MOSFET"
Solid-State Electronics, Vol. 44, Issue 9, 1 September 2000, pp. 1707-1710

C. Fink, K. G. Anil, H. Geiger, W. Hansch, J. Schulze, T. Sulima and I. Eisele
"Optimization of breakdown behaviour and short channel effects in MBE-grown vertical MOS-devices with local channel doping"
Thin Solid Films, Vol. 369, Issues 1-2, 3 July 2000, pp. 383-386

J. Kang, J, X. He, D Vasileska, D.K. Schroder
"Optimization of FIBMOS through 2-D device simulations"
Book of Abstracts. IWCE Glasgow 2000. 22-25 May 2000 pp. 87 -88

S. Williams and K. Varahramyan,
"New TCAD-based statistical methodology for the optimization and sensitivity analysis of semiconductor technologies"
IEEE Trans. Semiconductor Manufacturing, Vol. 13, May 2000, pp. 208-218

Yun-Gueon Shin and Jong-Hwa Lee
"A study of electrical characteristics and reliability on flash EEPROM cell"
Proceedings of the 4th IEEE Korea-Russia International Symposium on Science and Tech, Vol. 2, 2000

V. Narayanan et al
"Reduction of Metal-Semiconductor Contact Resistance by Embedded Nanocrystals"
Proc. IEDM 2000

K. G. Anil et al
"Role of Inversion Layer Quantization on Sub-Bandgap Impact Ionization in Deep-Sub-Micron n-channel MOSFETs"
Proc. IEDM 2000

Monfray S. Autran J.L. Jurczak M. Skotnicki T.
"Self-Consistent Optimization and Performance Analysis of Double-Gate MOS Transistor"
Proc. ESSDERC 2000, pp. 336-339

Tsamis C. Tsoukalas D. Tserepi A.and Tsoi E.
"The Influenceof Silicon Intersticial Clusters on the Reverse Short Channel Effect"
Proc. ESSDERC 2000, pp. 172-175

F. Roger et al
"New Calibration Method Of Analytical Models For Ion Implantation"
IWSM 2000, Honolulu, pp 18-21

M. Kataoka, K. Komuro, K. Fujita and A. Taniguchi
"Analysis of 0.5 m channel Al/WSix/Poly-Si gate performance in high-frequency band Si power MOSFETs with process/device/circuit continuous simulation"
Solid-State Electronics, Vol. 43, Issue 9, September 1999, pp. 1689-1694

G. Schrag, G. Zelder, H. Kapels and G. Wachutka
"Numerical and experimental analysis of distributed electromechanical parasitics in the calibration of a fully BiCMOS-integrated capacitive pressure sensor"
Sensors and Actuators A: Physical, Vol. 76, Issues 1-3, 30 August 1999, pp. 19-25

D. Munteanu, S. Cristoloveanu, and E. Guichard
"Numerical simulation of the pseudo-mosfet characterization technique"
Solid-State Electronics, 43(3):547-554, March 1999

G. -F. Dalla Betta, P. Bellutti, M. Boscardin, L. Ferrario, G. Soncini and N. Zorzi
"An all-implanted p-channel Si JFET fully compatible with CMOS technology"
Microelectronics Journal, Vol. 30, Issue 3, March 1999, pp. 281-285

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"Vertical p-MOSFETs with gate oxide deposition before selective epitaxial growth"
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