One of the critical aspects of bringing a new process into production is getting the foundation IP designed (at a minimum, standard cells and SRAM memories). The dominant digital design methodology today is to use synthesis and automated place & route to assemble these. Very little design can take place until these elements exist and have been fully characterized so creating these libraries is a critical step in making a process usable for real designs.

Silvaco’s layout environment can be used for creating these cells, which are largely done by hand, although in a modern FinFET process the cells can have very stylized designs. Very accurate extraction can be done using a full 3D field-solver for both SRAM and standard-cells to ensure the most accurate parasitic values. Since almost all other parts of the design will be built on this foundation it is critical that precise values are obtained since errors will otherwise propagate.

Standard cells today require characterization at a very large number of process corners and needs to be automated. Characterizing a full standard cell library might take as many as 25,000 simulations. Silvaco provides an environment for automated standard cell characterization and SRAM characterization. For simulating a full SRAM (or other large extracted netlists) there is high-capacity parallel SPICE.

There is support for OpenAccess making it easy to interoperate with other design environments for the actual IP or SoC design to be done. For FinFET nodes (16nm) model validation is also done with foundry partners for SPICE simulation accuracy.

AccuCore Memory Characterization

In a modern process even a high drive buffer can overload a minimum width metal line and so it is very important to have power, EM/IR and thermal analysis for both block-level design and full-chip level design. Silvaco’s reliability analysis is certified by TSMC but can be used with any foundry.

 

InVar Power/EM/IR/Thermal Analysis

 

Capabilities

3D RCX
  • 3D Parasitic Extraction for SRAM and Standard Cells
SPICE Simulation
  • Parallel SPICE for high accuracy
  • FastSPICE for Large Extracted Post-layout Simulation
  • TSMC Model Certification for FinFET Nodes
  • Distributed Monte Carlo
  • Automated Standard Cell Characterization
  • Automated SRAM Characterization
Variation Analysis
  • High sigma analysis for bitcell (7ó), sense amp, array
  • Multiple failure zones, Binary/ bimodal distributions, non-linear behavior
  • Standard Cell library statistical functional verification
  • Fast Monte Carlo analysis to save simulation runs; Local mismatch analysis for ADC
  • Statistical corners for quick design iterations
Custom Design
  • Wide Range of Foundry PDK Support
  • OpenAccess iPDK Support
  • Full Custom Layout
  • Integrated Extraction and DRC/LVS
Extracted Netlist Analysis & Reduction
  • Parasitic Reduction
  • Design Analysis
  • Comparison of extracted netlist with parasitics
Invar
  • Block to Full-chip Level Analysis
  • Early layout IR/EM analysis
  • SPICE Accuracy
  • TSMC Certified
  • Integration with third party tools