S-Pisces is an advanced 2D device simulator for silicon based technologies that incorporates both drift-diffusion and energy balance transport equations. A large selection of physical models are available which include surface/bulk mobility, recombination, impact ionization and tunneling models. Typical applications include MOS, bipolar, and BiCMOS technologies. The capabilities of all the physical models have been extended to deep submicron devices, SOI devices, and non-volatile memory structures.

All measurable electrical parameters can be calculated. For MOS technologies these include gate and drain characteristics, subthreshold leakage, substrate currents, and punchthrough voltage. For bipolar technologies Gummel plots and saturation curves can be predicted. Other important characteristics that can be calculated include breakdown behavior, kink and snapback effects, CMOS latchup, guarding breakdown voltage, low-temperature and high-temperature operation, AC parameters, and intrinsic switching times.

Complete MOS Characterization

Above shows the electron temperature distribution in a 0.3µm MOSFET. The impact ionization rate is based on the carrier temperature rather than the local electric field.

Above shows the simulated snapback in the breakdown curve caused by the parasitic bipolar.

Above is the substrate current in a MOSFET calculated using the Energy Balance and classical drift-diffusion models. The behavior calculated using the Energy Balance model is in much better agreement with measured behavior as it includes velocity overshoot and non-local impact ionization.

The LDD MOSFET structure shown above was simulated in the process simulator ATHENA and the final structure imported directly into ATLAS. A drain voltage of 14.5 V was applied to the drain contact and the electric field contours superimposed on the plot.

The ID-VD and ID-VGS simulated data for different VGS and VBS respectively. These characteristics may be loaded directly into UTMOST and the equivalent BSIM3 or BSIM4 Spice model extracted. New technologies may therefore be characterized before any fabricated wafers are available.

Complete Bipolar Characterization

S-Pisces simulates all aspects of bipolar device performance. DC characteristics such as Gummel plots and I_c vs. V_CE are all easy to simulate. Transient calculation of intrinsic switching speeds and f_T vs. I_c are performed using the time domain mode of S-Pisces.

Simulated IC-VCE characteristics.

Simulated Gummel plot (IC and IB vs VB) and the current gain vs IC.

Intrinsic switching speed of a bipolar transistor by performing a transient analysis where the base voltage gets pulsed on.

Characteristics of AC performance to arbitrary high frequencies is possible. The figure above shows the cutoff frequency (fT) as a function of collector current. Current gain and other RF figures of merit can also be plotted against frequency.

A bipolar transistor was simulated in ATHENA and imported into ATLAS. Voltages were applied to the collector and base contacts to turn the transistor on. The figure illustrates the electron concentration contours and current flow vectors, when the device is operating.

S-, H-, Y-, Z- and ABCD- parameter analyses are supported. The figure above shows a Smith chart with the S11 and S22 parameters plotted on it. TonyPlot displays S-parameters using Smith charts and polar plots.

STET Device Structures

Enhancements to S-Pisces enable rapid and robust simulation of SOI transistors. Advanced numerical techniques are employed to enable fast calculation of all SOI characteristics including the kink effect. The figure above shows the impact ionization rate and current flowlines in a thin layer SOI transistor.

Above shows the ID-VD characteristics of the above device which illustrates both the kink effect and breakdown.

Above is a comparison of electron concentration in the off and on states in a power DMOS device. The left hand figure is for the off state with the gate voltage set to zero. The right hand figure is with a gate voltage well above threshold. The inversion layer can be clearly seen at the surface of the channel.

As an example of a hybrid device, an insulated gate bipolar transistor (IGBT), is shown above. Potential in the on-state and current flowlines are shown. An equal amount of current density flows between each pair of lines. The current flows from the emitter close to the surface, under the gate, and down into the collector contact on the backside.

S-Pisces includes models to support simulation of EPROMs, EEPROMs and FLASH EEPROM cells. Hot carrier injection and Fowler-Nordheim tunneling are used to charge and discharge the floating gate. The figure (above) illustrates potentials and ionization rate in a FLASH EEPROM cell prior to programming. The complex geometry is imported automatically from ATHENA.

EEPROM device design curves are shown in the three figures above. These show programming time vs. drain voltage, erasing time vs. gate oxide thickness and a programming ID/VDS curve showing punchthrough.

Parasitic Capacitance

MOSFET parasitic capacitances can be extracted for any device size. Complex effects such as the voltage dependence of overlap capacitance for an LDD structure are modeled. The figure above shows a gate C-V plot for a MOS capacitor. Both the high and low frequency responses are demonstrated.

For junction capacitance S-Pisces provides C-V data that can be used to extract SPICE circuit parameters. The above plot shows junctions capacitance CGD as a function of drain voltage VDS.

Breakdown Analysis

Breakdown voltages of power devices are improved using multiple guard ring structures. S-Pisces simulates the floating regions and allows the optimization of the numbers and spacings of guard rings. The figure above shows a structure with two guard rings which act to spread out the potential contours, thereby reducing the electric field and increasing the breakdown voltage.Using cylindrical symmetry, 3-D guard ring structures can be modeled. Another common technique to increase breakdown voltages is the use of floating field plates. These can be simulated in S-Pisces using models similar to EPROM floating gates.

Strained Silicon MOS

Comparison of in-plane and perpendicular electron mobilities in strained silicon on SiGe

Technical Specifications

S-Pisces calculate DC, AC and time-domain solutions for general nonplanar 2-D silicon based device structures. The device structures may be specified by the user, or from the output of a process simulator such as ATHENA. S-Pisces incorporates both drift-diffusion and energy-balance transport models, and provides many advanced mobility models. S-Pisces includes models for Shockley-Read-Hall and Auger recombination, band-gap narrowing, impact ionization, band-to-band tunneling, Fowler-Nordheim tunneling, non-local tunneling, hot carrier injection, Ohmic and Schottky contacts, and floating gates.

Rev. 012308_05