3D Non-Isothermal Device Simulator

The Giga 3D module extends Device 3D by incorporating the effects of self-heating into a device simulation. It includes models for heat sources, heat sinks, heat capacity and thermal conduction. Physical and model parameters become dependent on the local lattice temperature where appropriate, allowing the self-consistent coupling between the semiconductor device equations and the lattice temperature.

Key Features

  • Self-Consistent Lattice Temperature solver
  • Thermodynamically correct modelization
  • Coupled to Drift-Diffusion or Hydrodynamic equations
  • Able to model steady state, transient and small signal a.c. biasing
  • Default parameters for thermal conductivity over a range of materials
  • Default parameters for heat capacity over a range of materials
  • Lattice temperature dependence for a wide range of parameters
  • Joule and Peltier/Thomson heat generation terms
  • Flexible boundary condition specification
  • Choice of non-linear solvers for coupling to drift-diffusion equations
  • Anisotropic thermal conductivity tensor
  • Flexible thermopower specification, including phonon drag

Possible Uses

  • Analysis of ESD protection structures
  • Simulation of power devices such as rectifiers, thyristors, mosfets, bipolar transistors
  • Modeling LED, SOI , HBT, HEMT devices
  • Thermo-Voltaic device simulation
  • Thermal runaway modeling
  • Device efficiency modeling

DC Ohmic Heating

Giga 3D takes account of all forms of heat generation within the device. Joule heating, generation-recombination and Peltier Thomson heat effects are self consistently solved with all semiconductor and optical equations. Giga 3D can be used for all DC, AC and transient simulations. In Giga 3D’s simplest applications, such as for power devices, joule heating is often all that is needed as shown in the following examples.

Slice of a 3D cylindrical VDMOS structure created for Giga3D illustration. The gate oxide thickness is 50 nm and the silicon region is 4 microns long. Lattice Temperature of the VDMOS structure biased to its forward blocking voltage limit. The drain is a thermal sink and the source is constrained to be at 300 K.

 

Impact ionization generation rate near breakdown for the VDMOS structure. This occurs in the drift region between source and drain. The impact ionization model includes lattice temperature dependent coefficients.
Lattice temperature versus drain bias with the VDMOS biased into channel conduction mode. It also increases with gate bias due to the higher drain current this produces.

 

The total heat power generated in the VDMOS structure as seen in a 2D radial cutplane. The p-n junctions are also shown in this figure, the heat generation occurs mainly in the N- drift region and at the edge of P- base region. Device structure of a short channel ultra-thin SOI transistor with a body contact. The top oxide layer has been removed for clarity. Silicon thickness is 0.2 microns and effective channel length is 0.8 microns.

 

Lattice temperature distribution for the SOI transistor at a gate bias of 3 V and a drain bias of 4V. Typical characteristics for the SOI transistor are shown, both with and without the Giga 3D lattice temperature model enabled. With the increase of drain bias, lattice temperature increases leading to a reduction of the mobility and thus a reduction of the current. This phenomenon is called Negative Differential Resistance (NDR) and can only be correctly simulated in SOI devices with a lattice heating model.

 

Users can adopt either a thermodynamically correct lattice heating model or use field times current density as the heating term. The figure shows the difference between these two cases for a 1D slice through a 3D p-n junction diode in forward bias. The net doping profile is shown at the top, the electric field in the middle and finally the total heat power. Because the net current is diffusion dominated the product of electric field and current is negative over much of the junction. This can cause spurious cooling effects. Using the thermodynamically correct modelization avoids this problem.

 

Coupled Temperature and Capacitive AC Analysis

The following example shows Giga3D operating in AC analysis mode. Here you can see thee effects of transitory self heating resulting from an applied AC signal. The thermal response time shows how the equations take account of thermal heat capacity and conduction and how this effects the measured capacitance of the device under test.

Giga3Dcan also be used in transient mode to study the performance of ESD protection devices. In this case, Giga3D would be used in conjunction with MixedMode 3D to self-consistently solve the Atlas 3D device equations for the device under test, together with SPICE elements to represent the device giving rise to the electro-static discharge, usually a person or a metallic machine. There are industry standard SPICE resistor/capacitor models to represent these two cases.

Small signal a.c. interelectrode capacitance for a p-n junction diode with 1 Volt of forward bias. At low frequencies the a.c. lattice temperature is modulated by the a.c. driving voltage and modifies the capacitance. At higher frequencies the lattice temperature cannot respond to the driving voltage and the behavior is adiabatic. In this limit the capacitance becomes the same as that obtained without using Giga 3D.

 

Coupled Opto-Electronic and Self Heating Effects

The self heating effects due to generation-recombination within a device or the heat produced from optical recombination as a result of an external applied optical beam are all correctly accounted for in Giga. This enables the heat distribution within a device to be calculated during optical thermal annealing steps either from RTA lamnps or from a re-crystallization laser beam for example. In the following examples, self heating effects within a Light Emitting Diode (LED) are shown.

Temperature distribution of a GaN-InGaN-AlGaN LED structure. A bias of 6V has been applied between the electrodes A surface of constant heat power generated in the LED structure

 

Rev. 110613_02