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Spider

Place and Route Design Flow

Spider is a netlist-to-GDSII place and route design flow for mainstream physical design and implementation.

Key Features

• Physical Design Flow with n-layer design capabilities ensures the expandability and flexibility needed to meet your tapeout requirements
• Advanced Capabilities enabled by the direct database system permits unrestricted “on-the-fly” review and editing of design data and parameters without requiring time-consuming data import and export format translation
• Synthesis Support integrates with third-party tools and legacy data through support for industry standard formats
• Floorplanning with Mixed-Signal Support within the toolset includes automatic placement and “what-if” analysis giving designers an early assessment of timing & area and providing predictable design closure
• Placement Optimization features like its automatic net-length minimization algorithms optimize cell placement
• Automated CTS features of Spider enable Clock Tree (CT) and High Fanout Net (HFN) Synthesis
• Deep Sub-Micron (DSM) Routing on cost effective server farms
• RC & Timing Extraction incorporating both embedded SPICE and RC extraction engines eliminating the need for external tools

Physical Design Flow

• Physical layout with n-layer design capabilities
• User definable parameters with layout generation coding features
• Supports gate-array, structured-ASIC and standard-cell SoC design styles
• Facilitates control of every aspect of design process
• Highlight nets for review with ease

Advanced Capabilities and RC & Timing Extraction

• Direct database system permits unrestricted review and editing of design data and parameters avoiding time-consuming import and export
• Self-Checking Correct-by-Construction Methodology, warns of potential problems without external checking
• GUI and command-line interfaces with “replay” scripting for run-time automation
• Embedded SPICE and RC extraction engines

Synthesis Support

• Integrates with third-party tools and legacy data through support for industry standard formats
• Imports verilog and EDIF netlist and Liberty.lib timing library support
• LEF/DEF physical and technology library and design exchange format support

Floorplanning

• Automatic placement and “what-if” analysis with multiple physical cell-types
• Real-time netlist enforced layout and ECO processes assure error free connectivity control with on-line independent verification and correction utilities
• Built-in netlist, constraint, library and database checking and correction utilities assure valid place and route starting conditions and updates
• Logical hierarchy netlist management with automatic design partitioning and region controlled floorplanning
• Padframe generation with chip and macro power planning and generation
• Automatic utilization estimation and aspect ratio control
• Placement and routing obstruction control features including rectilinear support
• Displayed weighted flylines during floorplanning allow you to place blocks to correctly minimize congestion

Placement Optimization

• Automatic net-length minimization algorithms optimize cell placement
• 2D congestion map of placement
• Size and/or instance controlled clustering
• Programmable placement strategies permit mixed free-form and datapath-like cell placement methods

Automated CTS

• Enables Clock Tree (CT) and High Fanout Net (HFN) Synthesis
• Automatically optimizes insertion delay, skew and inter-clock skew
• Provides delay, transition, skew and load net details

Routing

• Performs automatic standard cell and padframe routing
• Deep Sub-Micron (DSM) design rules support
• Real-time design rule enforced layout and ECO processes assure error free geometry design with on-line independent verification and correction utilities
• Mark specific nets for advanced automatic rip-up and re-route without needing to completely re-run placement and/or routing on the entire design or area
• Programmable automated contour, embedded block, ring, strap and rail routers make power and ground design and editing a breeze
• Easily perform interactive editing of either power and ground or signal nets with advanced placement and routing editors
• Snap, select, split, move, add corners and change layers during routing simply and quickly

Easy to Use Solution

• Easy “what-if” floorplanning analysis capabilities and automatic layout generators
• Powerful UPI and scripting lets you create macros and advanced custom automation environments plus macro automation to simplify repetitive tasks
• Easily replace cells and update the netlist at any time in the design flow
• Simplified top-level assembly and planning with object snapping (gravity)

A screen shot of a routed example.

Spider Place & Route Design Flow

• Interfaces – script, macros and GUI
• Inputs/Outputs – GDSII, EDIF, verilog, LEF, DEF, Liberty .lib, SPICE, DSPF, SDF, SDC

Rev. 083110_07