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CLEVER:

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90 Day | 1 Year | 3 Year

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CLEVER

RC Extractor for Realistic 3D Structures

CLEVER is a physics-based RC extractor that uses GDSII mask data and process information to create a realistic 3D structure for MEMS, advanced CMOS, TFT, Memory cells, etc., using its built-in etch/deposit processor and optolithographical simulator. CLEVER back annotates extracted RCs into SPICE netlist.

Key Features

• True 3D field solver with advanced lithography and realistic etch deposition models
• Industry Gold Standard for most accurate R and C extraction
• No restriction on geometry size 65nm, 45nm and below
• Fast feedback for optimization of circuit performance as a function of back end process and layout parameters
• User selectable boundary condition, material property, and solution tolerance control
• Automatic back annotation of field solved resistances and capacitances onto extracted active device netlist for immediate SPICE analysis
• Only RC extractor in the industry capable of reproducing the lithographic effects of Optical Proximity Correction (OPC) sub wavelength effects, phase-shifts mask (PSM), misalignment, defocus, and delta (CD)
• Silvaco's strong encryption is available to protect valuable customer and third party intellectual property.

Deep Submicron CMOS

• Dual Damascene Process
• Realistic 3D back end process simulations and accurate interconnect simulation with user selected tolerance
• Accurate via detailed capacitance and process analysis of individual problematic features, such as 45 nm via structures

CLEVER Simulated Via Structure	Round and cone-shaped vias

Flat Panel LCD and TFT Circuits

• Special features to deal with high aspect ratio structure

Electric field distribution

Touch Panel

• Robust resistances and capacitances simulation and extraction for touch panel display
• Optional FAST and ACCURATE modes (custom designed for touch panel only) bring simulation time down to minutes

3D structure of touch panel device	Layout of touch panel device

SRAM and Flash Memory Cell

• CLEVER uses advanced 3D process simulation to convert SRAM layout into an accurate 3D representation of the SRAM cell
• Electrical field solutions on the realistic 3D geometry allow accurate extraction of parasitics

Lithographic effects on metal geometry can affect the resulting capacitance significantly.	Six memory cells or partially completed SRAM array after removal of oxide insulation. SEM photograph (IBM).
3D structure of the SRAM cell.

MEMS Simulation

• Systems-on-a-chip brings together silicon-based microelectronics with micromachining technology

Productivity and Versatility

• User-friendly set up of LVS rule and process definition command files
• Integrated layout editor enables easy placement of additional labels, nodes, and masks
• Automatic 1D, 2D or 3D mode of extraction
• Automatic electrode labeling for conductor labeled outside the boundary of the simulation
• Multiple dielectrics in vertical and lateral directions
• Low-K dielectric and copper damascene process
• Shallow deep trench isolation (STI)
• Supports CMOS, Bipolar, SOI, TFT, SRAM, and other processes
• Built-in features to add, move, or rename electrodes or to change electrodes from horizontal to vertical for more accuracy in resistance extraction
  
• Support for dummy conductor regions commonly generated in recent CMP processes
• Cyclic boundary condition to allow users to perform cyclic simulations

CLEVER Design Flow Versus the Traditional Flow

CLEVER in Full Chip Design

CLEVER Inputs/Outputs

Rev. 092211_26