Intuitive graphical interface for process layer description and test structure definition for beginner and experienced process technology developers

Full Chip LPE Rule File Generator

Exact physics based 3D RC field solver Clever, combined with powerful Design of Experiment (DoE) and scripting language, allows support for any full chip parasitic extractor. Exact delivers the most accurate interconnect models for nanometer semiconductor processes and generates full chip layout parameter extraction (LPE) rule files.

Key Features

  • Powerful 3D field solver supports non-planar semiconductor profiles for accurately modeling irregular etch profiles, dual damascene, and low-K dielectrics
  • 3D field solver calculates interconnect capacitance models to deliver highest accuracy LPE rule files without compromising extraction performance
  • Intuitive and user-friendly graphical interface for process layer description and test structure definition for beginner and experienced process technology developers
  • Standard mode of operation handles most conventional processes whereas advanced mode can be used for more complex and non-planar process definition
  • Powerful scripting language allows data manipulation into any format

 

Front-end to Exact. Multilevel metal process with conformally deposited, non-planar multiple dielectrics.

 

Ease of Use and Adoption

  • Automatic deck generation and submission to 3D field solver
  • Menu-driven parameterized layout generator for test structure and pattern generation
  • Easy LPE rule file generation with Lisa scripting language
  • Flexible architecture for fitting raw parasitic data into a wide range of custom equations for xCalibre, Calibre xRC, Diva/Dracula LPE, and Hipex.
  • Process and layout preview

Productivity and Versatility

  • Batch mode option allows automated re-characterization runs
  • Advanced mode operation gives experienced user access to the more advanced process models
  • Ability to perform statistical analysis on capacitance variations
  • Easy to understand extracted capacitance tables that facilitate the analysis of the experiment
  • Worksheet/Optimizer
  • Support Multi-processor machines
  • Auto selection of 1D/2D/3D modes
  • Layer specific D.O.E. combinations to reduce simulation time
Example test structure created and used in Exact. Exact allows easy creation of parameterized layouts for any test structure to be used in the Design of Experiments.

 

Comparison of the original Exact capacitance data and the equation used to fit the data which has the optimized coefficients Optimizer window that allows interactive control of the fitting process.

 

Advanced Semiconductor Process Support

  • Interconnect parasitic capacitance modeling support for
  • Planar and non-planar dielectrics
  • Low-K dielectric and copper damascene process
  • Conformal dielectrics deposition
  • Sub-wavelength lithographic effects due to optical proximity correction (OPC)
  • Process variations impact on interconnect capacitance
  • Statistical analysis and worst-case parasitic analysis by applying known process margins to extracted data
  • Powerful 3D solver supports non-planar semiconductor profiles for accurately modeling irregular etch profiles, dual damascene, and low-K dielectrics
  • 3D field solver calibrates interconnect capacitance models to deliver highest accuracy LPE rule files without compromising extraction performance
  • Built-in Optimizer enables improved fitting and process optimization
  • Ability to simulate dummy metal
The Exact worksheet showing the data from the experiment.

 

Mentor Graphics xCalibre/Calibre xRC rule file generated by Exact.

 

Variation of capacitance coefficient with process variables can be seen graphically in Figure (a) (left) or analyzed statistically as shown in Figure (b) (right). The histogram shows the expected distribution in lateral capacitance with known margin on metal geometry.

 

Exact Inputs/Outputs

Rev. 061913_30