Guardian

3 Year Development Roadmap

Guardian DRC

• Improve performance of density check
• Support for mathematical expressions in density check
• Hierarchical DRC
• Redesign of complex non-orthogonal geometry process
• Approximation of skew edges by sequences of orthogonal or 45-degree edges
• Resizing text in layout
• Definition of polygon having the given coordinates on the specified layer
• Definition of specified text having the given coordinates on the specified layer
• Definition of a layout text in the file
• Exclude shapes and text objects from layout that occur in windows formed for each cell specified by cell name
• Exclude shapes and text objects from layout that occur in windows formed for each layer specified by layer name
• Include shapes and text objects in layout that occur in windows formed for each cell specified by cell name
• Include shapes and text objects in layout that occur in windows formed for each layer specified by layer name
• Selection of layer polygons that belong to a net having a total area on the layer conforming to the constraint
• Selection of layer polygons that have edges or edge segments on other layer
• Selection of orthogonal rectangles if they have the specified number of other orthogonal rectangles within a specified distance
• Selection of layer polygons that intersect the positions of text objects having a specified name
• Selection of layer polygons that satisfy the width constraint

Guardian LVS

• Device reduction effective property computation using LISA procedures
• Parallel/series merge and reduction of devices with consideration of specified parameter threshold
• Processing of primitive subcircuits
• Consider split gate ratio property in split gate structures
• Ignore specified nodes during LVS comparison process
• Creation of logic gates based upon tolerances of transistor parameters
• Flattening of internal hierarchy for given HCells during HLVS comparison
• Interpretation of subcircuits as distinct when names are the same but numbers of pins are different
• Reestablish hierarchical structure of netlists on base of logic gate recognition

Guardian NET

• Support layer prioritization functionality in connect statements
• Ability to rename specified layout cells
• Black boxing in hierarchical netlist extraction
• Enhance netlist extraction when connectivity problem with power or ground nets is detected
• Layout text ignore capability to disregard text labels in layout for specified cells
• Expand functionality for calculation of MOS device well proximity and advanced STI stress effect parameters used in 90 nm and below technologies
• Improve processing of hierarchical violations

Last Revised 05/17/2012