Roadmap

Catalyst AD

Development Roadmap

  • Unify Catalyst AD and AccuCore netlist and partition processing
  • Support for Liberty format equation syntax (cfg_gen setup automation)
  • Expand hierarchical processing methods and output results
  • Expand support of buses and buspins in Verilog netlists
  • Augment passgate circuit processing to increase characterization accuracy between partitions

Last revised November 12th, 2013