AccuCore

Block Characterization, Modeling and STA

AccuCore XT™ performs block level characterization and block/full chip static timing analysis (STA) of multi-million device circuits. This is mainly applicable for SRAM characterization.  AccuCore XT generates LibertyTM (.lib) files, Verilog connectivity netlist file for the cells in the design, a SPICE deck for critical paths and clock trees, and STA path reports including slack path and constraint check analysis. The inputs are SPICE and gate level Verilog netlists, which may include SDF with parasitic RC information, SPICE models, and user controls.

AccuCore XT is tightly integrated with the SmartSpice circuit simulator for accuracy and fast characterization, and also supports other SPICE simulators like HSPICE and Spectre.

Introduction

Using traditional gate level cell library-based static timing analysis for block level characterization typically means long characterization times. This is due to run-time complexity of characterizing all possible cells under all possible output loads and input slew conditions. In addition, there is potential accuracy loss, including table interpolation errors, routing dependent RC effects, IR drop, and well proximity effects.

AccuCore XT was developed expressly to efficiently and accurately automate block level characterization and perform block and full chip static timing analysis. It uses actual circuit loads, slews, and RCs for both signal and supplies, performing rapid and accurate automated characterization that considers all in-circuit effects.

AccuCore XT first reads the input files defining the block to be characterized and performs automatic partitioning. This is key to AccuCore XT’s efficient simulation and timing analysis performance. It derives the logic functions directly from the input descriptions, and generates vectors for SPICE simulation that are optimized for fast runtime. During characterization, the process files, partitioned netlists, optimized vectors and timing measurement requirements are passed to SmartSpice or other simulator to determine measured result values. Note that all results are generated by a full SPICE analysis of each partitioned block using actual circuit transistors, not an approximated model. The result is extremely accurate timing characterization.

In the modeling step, AccuCore XT utilizes the measured timing data created during characterization and generates the user-specified model types and formats.

For static timing analysis, AccuCore XT again uses all the characterization information to analyze the design. Libraries are used with conjunction with a structural Verilog netlist for timing and connectivity. Paths are traced and compared with expected arrival times.

Features

  • Generates LibertyTM (.lib) and .sdf timing models, gate-level Verilog netlist. Also generates/reads DSPF and .sdf files for STA
  • Exports fully sensitized SPICE decks for selected critical paths and clocktrees with measurements
  • Automatically partitions blocks into cells
  • Automatically extracts cell functions and generates vectors required for accurate SPICE characterization
  • Fast API based integration with SmartSpice
  • Complete block and full-chip gate level STA environment for rapid bottleneck analysis and timing verification
  • Powerful command set enable mixing both custom and ASIC/SoC functions in a single analysis environment
  • Automated setup & hold, delay and skew characterization of SRAM critical paths & timing arcs

Benefits

 Setup and scripting capabilities:

  • Automated .lib to .cfg import for easy setup and scripting with various .cfg validation options
  • Supports full case sensitivity flows
  • Supports both flat and hierarchical design flow
  • Advanced RC mode for efficient handling of large designs
  • Advanced slope propagation and threshold management options
  • Supports various user defined loading methods
  • Automatic hierarchical and flat netlist partitioning of blocks to cells with advanced user override options
  • Dedicated RAM/CAM partitioning with sense amp and read/write cycle options
  • Advanced strength and state-based function extraction features
  • Automatic clock propagation with advanced user overrides
  • Supports user defined input vector constraints
  • Advanced debugging and design reporting options for quick root-cause analysis

Characterization and modeling capabilities:

  • Cell matching improves reuse and incremental update capabilities
  • FAST_MODE option for fast prototyping analysis
  • ASIC flow option for easy standard cell-based flows
  • Automatic input capacitance characterization method
  • Automatic setup and hold, recovery and removal and minimum pulse width characterization and user defined override options
  • Automatic vector ordering and sizing with user override
  • Advanced one-time multi-corner, multi-mode full path model characterization for fast STA
  • Supports direct simulator option control with defaults
  • Generates gate-level Verilog netlist and timing models with output format options
  • Automatic partitioning and characterization of 6T and 8T SRAM bit cells

Block-level STA capabilities:

  • Enables gate-level timing checks of custom transistor level designs
  • Utilizes advanced path tracing algorithms of longest and shortest paths
  • Performs both critical and subcritical method of tracing to avoid multi-layer timing problems
  • Automatic false path elimination
  • Numerous path limiting and pin, net and arc based timing blocking options
  • Performs function-based clock and constraint propagation reducing ECO re-analysis ripple-effects
  • Supports various design styles of both static and dynamic logic, latches, flip-flops, muxes, and tristate circuits
  • Built-in timing checks simplify constraint specification
  • Analyzes gated and multi-frequency clocks across multi-cycle paths
  • Permits customized gated clock, data-to-data and clock-to-data path timing checks
  • Supports DSPF and SDF back-annotation
  • Performs bottleneck analysis of arrival and required path net and pin based timing requirements
  • Permits separate multiple rise and fall edge timing specifications common in footless logic

Full-chip STA Capabilities:

  • Concurrently performs both block-level and full-chip STA
  • Generates compressed, ring/interface and blackbox timing models
  • Supports hierarchical verilog and mode-based multi-corner analysis
  • Supports both DSPF and SDF back-annotation
  • Enables constraint management, block-level constraint generation and slack allocation for hierarchical design methods
  • Permits user-specified uncertainty and skew relationship driven timing analysis with common path optimization
  • Advanced debugging features for clock waveform and clock propagation
  • Advanced debugging features for netlist, library and analysis verification
  • Tcl API interface for custom reporting and analysis functions

 

Applications

  • Block/Macro characterization & SRAM characterization

Technical Specifications

  • Input/output formats supported: LibertyTM (.lib), Timing models (.sdf), gate-level Verilog netlist (.v), DSPF, SPICE netlist, SPICE models, Timing path reports, SPICE deck of clock trees, SPICE deck of critical path, .tcl files
  • Supported SPICE simulators: SmartSpice, Eldo, HSPICETM, SpectreTM