Digital tools for cell library characterization, large core STA, Verilog simulation, fault analysis, placement and routing.

HyperFault

HyperFaultMixed-Level Fault Simulator. Verilog IEEE-1364-2001 compliant fault simulator that analyzes test vectors’ ability to detect faults. Supports mixed levels of gate, behavioral, and switch with SDF timing.

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Catalyst AD

Catalyst DASPICE Netlist to Verilog Gates Converter. The premier tool for converting transistor-level designs into verilog gate-level representations with applications in microprocessor, DSP, graphics and high-speed communication markets.

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Spider

SpiderPlace and Route Design Flow. Netlist-to-GDSII place and route design flow for mainstream physical design and implementation.

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Silos

SILOSVerilog Simulator. Easy-to-use IEEE-1364-2001 compliant Verilog simulator. An industry standard since 1986, its debugging features provide a productive design environment for FPGA, PLD, ASIC and custom digital designs.

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Catalyst DA

Catalyst ADVerilog Netlist to SPICE Netlist Converter. Translates a structural Verilog netlist into equivalent SPICE format netlist to be used for layout verification or SPICE simulation.

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