Multiple parasitic extraction models, including lumped RC, C only, R only, coupled C and fully distributed RC

Full-Chip Parasitic Extraction

Hipex™ provides an accurate and fast solution for the extraction of parasitic capacitance and resistance from hierarchical layouts of analog, mixed-signal, memory IC and SoC designs. As part of Silvaco’s complete Physical IC design Verification flow, it is tightly integrated with Expert layout editor for DRC/LVS and RC parasitic extraction.


As advanced semiconductor processes geometries continue to shrink and add metal layers, the need to accurately model device behavior and validate design performance is crucial. Further, today’s designs require accurate modeling to help designers reduce power consumption and silicon area.

Working from GDSII, cell netlists and rules-based technology files, Hipex extracts very accurate parasitic resistance and capacitance values from the layout. It performs the extraction for full chip or selected nets or nodes, then back-annotates the schematic netlist with the exacted parasitic. 

The device extraction capabilities of Hipex allows the generation of hierarchical netlists that preserve the original layout hierarchy and supports a wide range of standard and parameterized user-defined devices. In addition it performs electrical rule checking (ERC) for shorts, opens and dangles.

Built for efficient parallelization on multi-processing servers, Hipex is fast and has efficient memory usage for large, full chip designs. Using Hipex together with Silvaco’s additional extraction tools Exact and Clever, the accuracy can be further fine-tuned to include support for 3D extraction.


  • Wide range of different parasitic extraction models, including lumped RC, C only, R only, Coupled C and fully distributed RC is supported
  • Back-annotates the extracted netlist with Schematic nodes, parasitic resistance and capacitance
  • Non-shielded lateral (multilateral) and Corner capacitance model
  • Accurate device extraction for non 45 and non 90 degrees devices and arbitrary shape resistors using multiple extraction models and equation solvers
  • Enables total per net capacitance and point-to-point resistance calculation by providing extracted parasitic RC in CSV format
  • Automated back annotation to Expert layout editor for accurate post-layout simulation, analysis and visualization of parasitic
  • Field solver mode generates accurate parasitic resistance calculation and addition of 3-layer configurations and regions with numerous contacts
  • Supports custom technologies including LCDs
  • Unique extraction algorithm allows to extract non-default geometric parameters (such as enclosure vectors) used to define custom capacitance models        
  • Scripting language for custom rule creation


  • Performance of a fast 2D extractor with capacitance calculation near 3D accuracy
  • Fast analysis of user selected critical nets or layers without extracting the whole chip in SoCs and large memories
  • Efficient network reduction using time domain and scattering parameter based macro-modeling methods

Figure 1: Visualization of Hipex Extraction 


  • Analog, Mixed-signal, Memories, SoC designs

Technical Specifications

  • Input files to Hipex: Layout files(GDSII,ELD,OA), Technology Files (Extraction rules), Schematics and Pre-extracted netlists
  • Output files from Hipex: SPICE Netlists with Parasitic RC, DSPF, SPEF, CVS netlists