SmartSpice

1 Year Development Roadmap, 2011

SmartSpice core

• Analog circuit synthesis
• Mixed language (Spectre, HSPICE, and SmartSpice) parser
• Topology check for floating circuit blocks
  

HSPICE compatibility

• .LIN analysis
• variation block
  

Spectre compatibility

• DC/AC match analysis
  

HSIM compatibility

• Circuit Checker
  

Verilog-A

• Migrate from Verilog-AMS LRM version 2.2 to 2.3

SmartView

• Port to 64-bit Windows platform
• Post processing digital and mixed-signal simulations
• JavaScript integration
• Advanced clock jitter measurement
• Display simulation statistical information