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CatalystAD:

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Release Notes (Since Baseline)

Release Notes (2012 Baseline)

Manuals

Product Roadmaps
90 Day | 1 Year | 3 Year

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CatalystAD is premier tool for converting transistor-level designs into verilog gate-level representations with applications in microprocessor, DSP, graphics and high-speed communication markets. CatalystAD can be used in place of Synopsys Pathmill, Synopsys Nanotime, Synopsys PrimeTime, Synopsys HSPICE, Cadence Encounter Timing System, Cadence SPECTRE, Magma Tekton, Magma Quartz Time and Mentor ELDO. It provides the following key features:

• Converts transistor-level designs into verilog gate-level representations
• Provides an automated solution for generating verilog netlists and models
• Provides reverse-engineering legacy hard IP, design reuse and migration logic
• Supports HSPICE˙/SPECTRE˙ and DSPF hierarchical or flat netlists
• Handles all classes of CMOS/SOI design styles
• Controls proper modeling of wide fan-in pass-gates of 24 inputs or more
• Communicates with AccuCore to provide verification and timing modeling
• Supports hierarchical or flat SPICE netlist
• Uses enhanced configuration to set variables and direct the behavior
• Uses a user-friendly TCL script command file to read and generate the model
• Generates structural verilog netlist
• Generates report log file and some cross-reference files
• Uses in microprocessor, DSP, graphics and communication applications

Synopsys Pathmill, Synopsys Nanotime, Synopsys PrimeTime, Synopsys HSPICE, Cadence Encounter Timing System, Cadence SPECTRE, Magma Tekton, Magma Quartz Time and Mentor ELDO are the trademarks of their respective owners.