DOWNLOADS | CONTACT US

Home

Product Map

Product Examples

TCAD

Analog / AMS / RF

	   Overview
	   Gateway
	   SmartSpice
	   Verilog-A Language
	   SmartSpiceRF
	   Harmony
	   UTMOST III     
	   UTMOST IV     
	   SPAYN     
  

Custom IC CAD

	   Overview
	   Expert
	   Guardian
	   HIPEX
	   ClarityRLC
  

Interconnect Modeling

	   Overview
	   EXACT
	   QUEST
	   CLEVER
	   STELLAR
  

Digital CAD

	   Overview
	   SILOS
	   HyperFault
	   AccuCell
	   AccuCore
	   CatalystAD
	   CatalystDA
	   Spider
  

Downloads & Support

Download & Support Supported Platforms

Licensing

	  Overview	  
	  TCAD Unlimited
	  Universal Tokens	  
	  Token Card	  
	  TCAD Omni 	  
	  Term-Based	  
	  Perpetual	  
	  EDA Academic Suite	  
	  

PDK Design Flows

	  Overview
	  Available PDKs
	  Foundry Partners
	  Quality and Testing
	  Maintainability
	  PDK Development Services
	  Documentation & Training
	  Migration to Silvaco PDKs  

Technical Library

  EDA Publications  
  TCAD Publications  
  Video Library

Services

	   Overview
	   TCAD Services
	   SPICE Modeling
	   Parasitic Extraction
	   PDK Development
	   Cell Libraries and Blocks
  

University Program

Government Programs

Locations/Contact Us

Corporate

	  About Us
	  News
	  Management 
	  Partners 
	  Careers
	  Conferences
	  Advertisements
	  Workshops
  

Product Roadmaps
90 Day | 1 Year | 3 Year

Verilog-A

3 Year Roadmap, 2009 - 2011

Multiple matrices support for improved simulation of circuit design with both high and low frequency analog content