SmartSpice 200

ANALOG CIRCUIT SIMULATOR – Fully Functional, Limited to 50 Elements

SmartSpice 200 is a fully featured version of the industry’s gold standard SmartSpice analog circuit simulator limited ONLY by a circuit size of up to 10 transistors and/or a total of 50 circuit elements, and/or 5 Verilog-A modules or subcircuit calls. It is ideal for faculty members, students, and designers of small circuits. SmartSpice 200 is fully integrated with Gateway and Gateway 200.

SmartSpice 200 is suitable for product evaluation, teaching, and training. It provides a convenient and fast Verilog-A based SPICE model development environment. The first commercially available, highly interactive circuit rubberbanding capability makes analog designs easier to create and visualize.

Key Features

  • 100% HSPICE™ and SPECTRE™ compatible for netlists, models, analysis features, and results
  • Provides the most accurate circuit simulation results for critical analog designs
  • Multiple solvers and stepping algorithms for robust convergence
  • Largest collection of calibrated SPICE models for traditional technologies (Bipolar, CMOS) and emerging technologies (TFT, SOI, HBT, FRAM, FinFET etc.)

 

Accuracy

SmartSpice 200 is the most accurate circuit simulator for critical analog designs incorporating nanometer effects.

  • Uses Gaussian elimination in an efficient matrix (based on the original Berkeley 3C1 solver)
  • A library of direct and iterative solvers
  • Verifies and validates Berkeley physics-based model parameters at run-time for continuity, linearity, and valid parameter range
  • Detects inconsistencies in poorly-extracted foundry models and prevents these errors from degrading the final product performance and accuracy
  • Offers a full set of options for controlling speed vs accuracy of simulations

 

Convergence

SmartSpice 200 selects the right solver for optimal convergence

  • Surveys initial conditions and iteratively sequences through a series of methods and algorithms to attain optimal convergence
  • Multiple solvers provide the best solver for a given circuit topology

 

Analysis

SmartSpice 200 offers user-defined support for analysis options

  • Stop/Continue Algorithm for transient analysis
  • Nested parametric analysis
  • Scoping of names used in netlist
  • Fast cell characterization via direct matrix access on the next parametric step
  • Sophisticated optimization at the sub-circuit level
  • SEE analysis using .RAD statement leveraging foundry supplied compact models
  • Equation editor for .MODEL parameters to support sub 65 nanometer designs

 

Ease of Adoption

Ease of Adoption into an Existing Design Flow: SmartSpice 200 fits your design flow and foundry models

  • SmartSpice can co-exists in an existing design flow implemented with HSPICE and Spectre
  • Supports foundry-supplied SmartSpice 200, HSPICE and SPECTRE models
  • Supports legacy netlists from HSPICE, PSPICE™, and Berkeley SPICE
  • Seamless integration with Cadence analog environment through ADE with SmartSpice run in Spectre compatible mode
  • This means you can run job submission software (LSF, Sun Grid, etc.) seamlessly
  • Seamless integration with Silvaco PDK-based analog/mixed-signal/RF tool flow

 

Model Development Capabilities

  • Core competence in SPICE modeling, data acquisition and model parameter extraction since 1984 with UTMOST for the highest accuracy in analog models
  • Verilog-A models offer fastest method for implementing Accellera standard electric-thermal models, sensor models, and other mixed physical effects
  • Silvaco offers accurate and prompt SPICE Modeling Services to extract DC, AC, S-parameters, capacitance, temperature, noise, and SPICE parameters over full temperature and corner models using statistical analysis

 

Models Available

BJT/HBT:

Gummel-Poon, Quasi-RC, VBIC, MEXTRAM, MODELLA, HiCUM, HiSIM-IGBT

MOSFET:

LEVEL 1, LEVEL 2, LEVEL 3, BSIM1, BSIM3, BSIM4, MOS 20, EKV, HiSIM, PSP, LEVEL 88, HiSIM HV, BSIM-CMG (FinFET), BSIM-IMG

TFT:

RPI poly-Si, a-Si TFT, UOTFT

SOI:

Berkeley BSIM3SOI, BSIMSOI4

MESFET:

Stats, Curtice I & II, TriQuint

JFET:

LEVEL 1, LEVEL 2

Diode:

Berkeley, Fowler-Nordheim, Philips JUNCAP/Level 500

FRAM:

Ramtron FCAP

 

Transient noise simulation: Voltage and noise waveforms at 2 different circuit nodes.

 

Inputs

  • Berkeley SPICE
  • HSPICE and SPECTRE netlists
  • W-element RLGC matrix files
  • S-parameter model files
  • Verilog-A

Outputs

  • Rawfiles, Output listings
  • Analysis results
  • Measurement data,
  • Portable across UNIX/windows platforms

 

Integrated Optimizer iterates device or model parameters to achieve target specifications in the form of DC, AC, transient curves, propagation delay, rise and fall times, power dissipation, etc. Sub-circuit optimization also available.

 

SmartView produces annotated plots and graphs of measurements of time, voltage, current, and power for rise time, slope, vector calculator, and eye diagrams from SmartSpice 200 and HSPICE simulation results.

 

Rev 022013_07