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InVar Reliability Analysis


Silvaco delivers a suite of tools devised for accurate and effective analysis of designs ranging from block level to chip level. The patented concurrent methodologies provide users the benefits of physical measurement accuracy without delays in runtime, yet also offer the ability of handling extremely large designs. For transistor level designs like analog blocks, high-speed IO's, custom digital blocks, memories, and standard cells, IR-drop and electromigration have traditionally been a bottleneck for physical verification within the EDA industry. Silvaco’s hierarchical methodology overcomes that hurdle and more accurately models IR-Drop, electromigration and thermal effects across all process nodes, including 20nm and FinFET.

Silvaco's solution utilizes only industry standard design file formats and thus creates a path for users to quickly learn the platform in a user-friendly environment designed to assist quick turn-around-times.

Silvaco tools were created with the idea of providing true power integrity from early power analysis to sign-off for digital, analog and mixed-signal designs.

Silvaco SmartSpice and Invar Electrothermal co-simulation flow


InVar Power™

The InVar Power™ is part of the industry's first real life accurate power analysis platform for custom and standard cell based designs. Faster, smaller and cheaper ICs built with expensive process technologies make little room for error, and re-spins are too costly. Silvaco customers are able to tapeout both analog and digital designs correctly and gain most with Silvaco’s solutions. Designers can no longer rely on previous generation of analysis/sign-off tools that do not provide complete and comprehensive verification (sign-off) solution. Designers need to understand and analyze all the various effects across the design including mutual dependency between power and thermal 2D/3D profiles, how dynamic thermal profiles affect device behavior in real time, how package, board and even neighboring elements affect realistic electro-thermal design simulation.

Silvaco's InVar toolset provides a solution that addresses demand for better accuracy and faster verification loops. Taking advantage of parallel processing and advanced algorithms we are able to deliver fast and accurate results matching lab measurements. The ability to scale to the largest SoC designs while maintaining SPICE level accuracy requires a fundamental change in processing information. Silvaco's solution supports power analysis at device, cell and IP/block levels. In case of presence of hierarchical structure of the design InVar Macro Modeling™ module allows to perform higherarchical analysis in one bottom-up run, accounting for changes in voltage and temperature throughout the hierarchical structure.

InVar EM/IR™

Reliable analysis of EM and IR problems is getting more and more challenging with advanced technology nodes and ever increasing design sizes. Where traditional tools lack scalability, only Silvaco's InVar EM/IR™ electromigration and IR-drop analysis for analog and digital ICs continues to scale with the complexity and feature size reduction required by modern IC development.

Silvaco provides simple and clear answers to the challenges. With quick and understandable setup it is possible to do analysis for multiple constraints - transient and static, for supply and signal nets in one fast run. Bringing analog and digital blocks together we get analysis to the new level of accuracy, there is no more need for multiple tools with separate and disconnected reports.

InVar EM/IR™ provides full visibility of supply networks from top-level connectors down to each transistor. Unique approach to hierarchical block modeling reduces runtime and memory and keeps accuracy of true flat run.

Correct support of fast-pacing EM rules represents one of the biggest challenges. Reliability rules are significantly different from fab to fab. This problem does not exist for current users of InVar EM/IR™. With flexible programmable implementation and direct support of fab rules user gets support for new rules the same day they get introduced.

One of the serious problems is a correct support of package models with number of supply pins in the 1000's with exploding die areas . It is not acceptable to reduce package supply to several RLC annotated virtual pins. InVar EM/IR™ supports RLCK annotation for every supply connector on the die providing ultimate level of accuracy for transient analysis.

EM problems that develop in real chips are often overlooked because of current analysis approach with corner temperatures, this never happens to our customers using InVar EM/IR™ unique feature of concurrent electro-thermal analysis. Any hotspot on the die is identified and EM constraints are calculated with accurate local temperatures. With any design size from tiny analog block to complex SoC we return reliability its original meaning.

InVar Thermal™

InVar Thermal™ provides the industry's largest capacity and most accurate thermal sign-off analysis available today. Silvaco solves the problem of miscorrelation with unique approach to analysis process that is scalable from few transistors to large blocks. Different analysis engines work in concert and take interdependence of power, device parameters, effective supply voltage, and temperature into account. Contrary to other tools, all types of analysis are performed in continuous temperature space across the chip. There are no predefined temperature corners for analysis.

InVar Thermal™ starts thermal analysis using thermal boundary conditions, environment temperature, and numerous thermal properties that can be individually defined for every material used in design. Analysis continues through fast converging iteration steps and comes up with unique temperature numbers for every device and routing object in the design. That means continuous 2D/3D analysis space for temperature. Patentable technique increases the speed and scalability of analysis engines and gives our customers significant time advantage. User can achieve accurate analysis results with InVar Thermal™ with less effort due to straightforward, natural flow and use of standard readily available design formats.

InVar Thermal™ reduces need for other analysis tools from multiple vendors, and our analysis results were verified in customer’s labs and outperformed other known thermal tools.

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Victory Process

3D Process Simulator

Victory Process is a general purpose 3D process simulator. Victory Process includes a complete process flow core simulator and three advanced simulation modules: Monte Carlo Implant, Advanced Diffusion and Oxidation, and Physical Etch and Deposit.

Victory Cell

3D Process Simulator For Large Structures

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Process Simulation Framework

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SSuprem 4

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Advanced Monte-Carlo Implantation Simulator

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Advanced Physical Etching and Deposit Simulator

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MC Etch & Deposit

2D Monte Carlo Deposition and Etch Simulator

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Advance 2D Optical Lithography Simulator

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Victory Device

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Device 3D

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Giga 3D

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MixedMode 3D

Circuit Simulation for Advanced 3D Devices

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Quantum 3D

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Luminous 3D

3D Optoelectronic Device Simulator

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3D Amorphous and Polycrystaline Device Simulator

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3D Light Emitting Diode Simulator

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Magnetic 3D

3D Magnetic Device Simulator

Magnetic 3D module enables the ATLAS device simulator to incorporate the effects of an externally applied magnetic field on the device behaviour.

Thermal 3D

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Device Simulation Framework

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Device Simulation Framework

Atlas enables device technology engineers to simulate the electrical, optical, and thermal behavior of semiconductor devices.


2D Silicon Device Simulator

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2D Device Simulator for Advanced Materials

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Non-Isothermal Device Simulator

Giga combined with S-Pisces and Blaze device simulators allows simulation of self heating effects.


Circuit Simulation for Advanced 2D Devices

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2D Simulation Models for Quantum Mechanical Effects

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2D Optoelectronics Device Simulator

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2D Amorphous and Polycrystalline Device Simulator

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2D Light Emitting Diode Simulator

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Organic Display

OLED and OTFT Organic Display Simulator

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Organic Solar

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Semiconductor Laser Diode Simulator

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Vertical Cavity Surface Emitting Laser Simulations

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2D Small-Signal Noise Simulator

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Ferroelectric Field Dependent Permittivity Model

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2D Magnetic Device Simulator

Magnetic module enables the ATLAS device simulator to incorporate the effects of an externally applied magnetic field on the device behavior.


Fast Simulation of FETS

Mercury is an ATLAS module optimized for the fast simulation of FETs. Mercury is physics-based and so can be used for the predictive simulation of devices.

MC Device

2D Monte Carlo Device Simulator

MC Device simulates the behavior of relaxed and strained silicon devices including non-equilibrium and ballistic effects in 2D.


Radiation Effects Module

The REM Radiation Effect Module allows Atlas 2D/3D and Victory 3D simulators to model total dose, dose rate and SEU effects in semiconductors through the generation of defect states, fixed charge, and charge transport within insulating materials.

Victory Stress

3D Stress Simulator

Victory Stress is a generic 3D stress simulator designed to calculate stresses, strains and mobility enhancement for 3D structures as well as stress evolution during multiple step process flows.


Interactive Deck Development and Runtime Environment

DeckBuild is an interactive runtime and input file development environment within which all Silvaco’s TCAD and several other EDA products can run.


Integrated Layout Editor

MaskViews is a simple to use, yet powerful layout editor that can read, write, create and edit layout files in either GDS2 or Silvaco’s layout format.


Structure and Mesh Editor

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1D/2D Interactive Visualization Tool

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TonyPlot 3D

3D Interactive Visualization Tool

TonyPlot 3D is a powerful graphics tool, capable of displaying 3D TCAD data generated by Silvaco TCAD process or device simulators and Silvaco's 3D parasitic products.



VWF is software used for performing Design of Experiments (DOE) and Optimization Experiments. Split-lots can be used in various pre-defined analysis methods.


Schematic Editor

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Analog Circuit Simulator

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Verilog-A Language

Source, Compiled and Encrypted

The Verilog-A language when combined with SmartSpice can provide circuit designers the ability to write custom models and verification of complex designs.

SmartSpice RF

Frequency and time domain RF circuit simulator

SmartSpice RF combines Time-Domain Shooting and Frequency Domain Harmonic Balance methods to provide accurate simulation of RF circuits.


Analog/Mixed-Signal Simulator

Hamony is an analog/mixed signal simulator that provides all the capabilities of SmartSpice and Silos and through this give the accuracy, performance, capacity and flexibility to simulate circuits expressed in Verilog, SPICE, Verilog-A and Verilog-AMS.

Utmost III

Device Characterization and modeling

Utmost III generates accurate, high quality SPICE models for analog, mixed-signal and RF applications.

Utmost IV

Device Characterization and SPICE Modeling

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Statistical Parameter and Yield Analysis

Spayn is a statistical modeling tool for analyzing variances from model parameter extraction sequences, electrical test routines, and circuit test measurements.


Power - EM/IR - Thermal

Silvaco’s realibity analysis methodology answers design challenges and more accurately models IR-Drop, EM and thermal effects across all process nodes.


Layout Editor and Viewer

Expert is a high performance hierarchical IC layout editor with full editing features, large capacity and fast layout viewing.


DRC/LVS/NET Physical Verification

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Full-Chip Parasitic Extraction

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Clarity RLC

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Full Chip LPE Rule File Generator

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3D RF Passive Device Modeling

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RC Extractor for Realistic 3D Structures

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3D Physics-Based RC Extractor for Large Cells

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Verilog Simulator

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Mixed-Level Fault Simulator

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Cell Characterization and Modeling

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Block Characterization, Modeling and STA

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Catalyst AD

SPICE Netlist to Verilog Gates Converter

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Catalyst DA

Verilog Netlist to SPICE Netlist Converter

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Place and Route Design Flow

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