EM/IR, Thermal Reliability and Power Integrity

Silvaco’s InVar™  performs power, EM/IR and thermal analysis on analog, digital and mixed-signal IC designs. InVar Prime, InVar Power, InVar EM/IR and InVar Thermal form a comprehensive power integrity solution for both early and final sign-off analysis. Power integrity analysis has been typically performed only later in the design cycle where schedule pressures are immense and the range of available design choices is sometimes constricted. InVar Prime provides the ability to perform early analysis on the design, yielding greater design freedom and fewer issues late in the process.


Analysis of IR-drop, electromigration and thermal effects have traditionally been a significant bottleneck in the physical verification of transistor level designs such as analog circuits, high-speed IOs, custom digital blocks, memories and standard cells. This is due to the need for accurate and increasingly complex analysis to be performed on designs that are progressively larger in size. For example, FinFET’s increased current density and thermal profile raise electromigration and EM failure rate probabilities that must be managed with careful analysis and design. 

InVar’s hierarchical methodologies overcomes these hurdles and accurately models IR-Drop, electromigration and thermal effects for designs ranging from single block to full-chip. Its patented concurrent electro-thermal analysis performs simulation of multiple physical processes together. This is critical for todays’ designs in order to capture important interactions between power and thermal 2D/3D profiles, examine how dynamic thermal profiles affect device behavior in real time and how package, board – and even neighboring elements – affect simulation results. InVar utilizes true spice electrical engine, not simplified device models, for precision and applies parallel processing technics to achieve performance. The result is physical measurement-like accuracy with high speed even on extremely large designs and applicability to all process nodes including FinFET technologies.

For a broad range of designs including processors, wired and wireless networks, sensors, high current ICs, sensors and displays, Silvaco’s InVar provides a user-friendly environment designed to assist quick turn-around-times and trouble free tape-outs. 



  • InVar Power helps designers understand and analyze various effects across design caused by mutual dependency between power and thermal 2D/3D profiles and how dynamic power dissipation affect device behavior in real time

  • InVar EM/IR provides comprehensive analysis and retains full visibility of supply networks from top-level connectors down to each transistor. Unique approach to hierarchical block modeling reduces runtime and memory and keeps accuracy of true flat run. Programmable EM rules enable easy adaptation to new technologies

  • InVar Thermal scales from single cell design to full chip and provides lab-verified accuracy of thermal analysis. Feedback from thermal engine to power and EM/IR engines provides unprecedented overall accuracy


  • Accuracy verified in lab and foundries
  • Full chip sign-off with accurate and high performance analysis
  • Analysis available early in the back end design, when more design choices are available
  • Pre-characterization not required for analysis
  • Easy learning curve
  • Effective prevention of power integrity issues
  • Broad range of technology nodes supported


  • InVar Prime – Early design stage power integrity analysis solution for Layout Engineers. Designers can estimate power, EM/IR and thermal conditions before sign-off stage. It helps in finding and fixing issues that are not detectable with regular LVS check like missing vias, isolated metal shapes, inconsistent labeling and detour routing.
  • InVar for Transistor level- The transistor-level solution is the only sign-off tool for analog designs that performs concurrent power, thermal and EM/IR checks
  • InVar for Gate level- Full-chip analysis/sign-off using concurrent analysis of power, thermal, EM/IR on block to full-chip level design

Technical Specifications

  • Input data required for InVar Prime
    • Layout- GDSII
    • Technology- ITF or iRCX
    • Supplementary data- Layer mapping file for GDSII, Supply net names, Locations and nominals of voltage sources, Area based current consumption for P/G nets
  • Input data required for transistor level designs
    • Layout- GDSII
    • Netlist- SPICE+DSPF
    • Technology- ITF or iRCX
    • Supplementary data- Layer mapping file for GDSII, Supply net names, Location and nominals of voltage sources
  • Input data required for gate level designs
    • Design data- LEF, DEF or Verilog
    • Models- Liberty
    • Timing- SDC
    • Parasitic file- SPEF
    • Technology- ITF or iRCX
    • Activity- FSDB, VPD, SAIF, VCD