More About HiSIM HV

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HV MOS
BSIM3-based High Voltage Compact Model

BSIM3v3.2.4
Industry Standard Sub-0.13 Micron
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BSIM3SOIv3.2
Industry Standard
SOI Model

BSIM4v4
Industry Standard
Sub-0.13 Micron
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EKV
Low Power MOSFET Model

HiSIM
Surface Potential-
Based MOSFET Model

Mextram
General Purpose Bipolar Model

Modella
Lateral PNP Bipolar Model

Mosvar
PSP-Based MOS Varactor Model

UOTFT
Universal Organic TFT Model

VBIC
Advanced BJT and HBT Model

HiSIM HV

Surface Potential-Based HV AND LDMOS Compact Model

Accurate SPICE Simulation of HV and LDMOS Devices Without Using Macro-Models

HiSIM HV is a surface potential-based model for high-voltage MOSFET devices. The model considers both the symmetrical device structure (HVMOS) and the asymmetrical laterally diffused device structure (LDMOS). All the features of the HiSIM-bulk MOSFET model are preserved in HiSIM HV with extensions mainly to include modeling of the drift region.

Features

The surface potentials along the device surface, including the drift region resistance effects, are calculated iteratively inside the model. This allows a single formulation of model equations to describe the device characteristics and ensures consistent computation of IV and capacitance curves.

• Complete surface-potential-based model
• Considers both symmetrical (HVMOS) and asymmetrical (LDMOS) device structures
• Quasi-saturation effects
• Self-heating effects
• Drift region resistance
• Capacitance including Cgd fall-off
• Impact-ionization effects in the drift region
• Bias-dependent overlap capacitances
• Diode current and capacitances
• Source and drain resistances
• Temperature dependence
• Universal and high-field mobilities
• Channel-length modulation
• 1/f, Thermal and Induced gate noise
• Smooth and continuous derivatives for fast and accurate simulation convergence
  

Asymmetrical (LDMOS) device cross-section.

Silvaco Implementation

• HiSIM HV is implemented as a member of ModelLib, Silvaco’s compact SPICE model library. It can be accessed within SmartSpice as LEVEL=62, 172. LEVEL=62 includes Silvaco enhancements for convergence with consistent results with the original STARC released codes (LEVEL=172)
• Linked to advanced convergence algorithms available in SmartSpice
• Internal warnings and diagnostic provide valuable information to help find convergence issues.
• Device internal variables (currents, conductances, capacitances) can easily be accessed like any other model parameter
• HiSIM HV is compatible with VZERO and BYPASS option in order to achieve great speed performance
• HiSIM HV is compatible with parallel architecture algorithms
  

Schematic diagram of HiSIM HV potential distribution for LDMOS case.

Benefits From Using HiSIM HV

• Single global parameter set – With model scalability, HiSIM HV requires only a single global parameter set for different device geometries. Owing to its surface-potential description, the use of nonphysical parameters is greatly reduced
• Fast simulation time – HiSIM HV enables fast simulation of circuits because it eliminates the use of sub-circuits typical in macro-modeling. The model is stand-alone and instantiated only once for an HV or LDMOS device
• Complete description of HV or LDMOS device characteristics – All principal device model features required by the Compact Modeling Council (CMC) are included in the model. Its surface-potential approach makes it flexible to include variations in HV or LDMOS structure

ATLAS (2D device simulator) and HiSIM HV typical drain current characteristics for LDMOS case. HiSIM HV models the self-heating effect and impact-ionization in the drift region.

ATLAS 2D device simulator and HiSIM HV Cgg and Cgd plots for LDMOS case. HiSIM HV predicts the Cgd fall-off.

CMC QA Test Suite Available in SmartSpice

The Compact Model Council (CMC) QA test procedures developed for verifying the correctness of HiSIM HV’s model definitions are included in a standard SmartSpice package. The procedures contain test variants designed to check HiSIM HV model parameter sets and model features. User’s guides are provided or easy test execution and customization depending on device and circuit engineers’ requirements.

CMC retains full ownership of QA procedures. For complete description, refer to www.geia.org. The procedures are available in SmartSpice as <S_INSTALL_ROOT>/examples/smartspice/CMCQA.

Additional LDMOS Model Postings on CMC Website

High quality presentations on the physics of the model, LDMOS parameter extraction, and model impact on circuit performance presented during the process of model nomination for standardization can be viewed here.

References

1. HiSIM HV 1.0.1 User’s Manual, Copyright 2008, Hiroshima University and STARC.
2. M. Yokomichi, et al., “High-Voltage MOSFET Model with Consistently Determined Potential Distribution in MOS Channel and Drift Region,” Proc. Int. Workshop on Compact Modeling 2008.
   

Rev. 062308_05