LEVEL=88

COMPACT HIGH VOLTAGE MOS MODEL

High Voltage PDK-based Design Tool Suite offers an integrated design flow solution for the design of LCD drivers, TFT drivers, automotive, industrial, motor control, and power management ICs for laptops, PDAs, and other battery operated electronics. The design flow is supported by Silvaco’s proprietory high voltage SPICE Level=88 model.

Key Features

  • BSIM3-based Level 88 SPICE model has the best high voltage model features include self heating, forward and reverse mode, asymmetry of parasitics, and Rds bias dependency
  • Utmost IV Model Parameter Extraction Software extracts highest accuracy SPICE models
  • Foundry partners support SmartSpice models and Silvaco PDKs
  • Silvaco offers fast development of large and complex PDKs
  • Same design environment across Unix, Linux, and Windows platforms

Gateway Schematic Editor

  • Powerful schematic capture and editor functionality to create and modify multi-view, multi-sheet, hierarchical IC designs
  • Seamless integration with SmartSpice Circuit Simulator that creates an interactive design environment with behavioral models, cross- probing, waveform display, and analysis
  • Controls multi-user projects with shared work spaces for libraries of cells and symbols used by the design team
  • Smooth transition from other schematic capture tools – out-of-the-box setup with no consultants needed, supports EDIF input
  • Easy to use at all skill levels – with online help for new users
  • Productive analog design environment offers parameterized cells (Pcells), automatic symbol generation, real-time simulation viewing (marching waveforms), and multi-user schematic locking

 

Standard BSIM3.

 

BSIM3 Level 88 with 9 additional parameters.

 

Level 88 additional 9 parameters provide the following physical effects:

  • Self-Heating
  • Asymmetry and bias (Vds) dependence of external resistance Rds
  • Dependence of mobility degradation on Vds
  • Subthreshold slope and reverse short-channel effect
  • Dependence of Vsat on Vgs and Vbs
  • Transconductance Gm reduction in saturation at high Vgs
  • Bias dependent saturation velocity
  • Asymmetry of all parasitics (Diodes and Resistance)
  • Forward and reverse modes of operation

 

LDMOS Surface Potential Based Compact Model

  • Accurate SPICE Simulation of LDMOS devices without using macro-models
     
  • Philips MOS20 provides a high-voltage-based LDMOS compact model that includes physical effects for both channel region and drift under the gate
     
  • LDMOS model is suitable to simulated lateral (LDMOS), Vertical Double-diffused (VDMOS) as well as Extended-drain (EDMOS) devices

SmartSpice Analog Circuit Simulator

  • 100% HSPICE™ compatible for netlists, models, analysis features, and results
  • Provides the most accurate circuit simulation results for critical analog designs
  • 8x - 12x faster than any true SPICE circuit simulator and the only SPICE supporting multiple threads for parallel operation
  • Multiple solvers and stepping algorithms for robust convergence
  • Largest collection of calibrated SPICE models for traditional technologies (Bipolar, CMOS) and emerging technologies (TFT, SOI, HBT, FRAM, etc.)
  • Provides open model development environment and extensive analog behavioral capability with Verilog-A option
  • OASIS is not used for the current interface to Cadence
  • Offers a novel transient non-Monte Carlo method to simulate the transient noise in nonlinear dynamic circuits
Lateral PNP transistor.

 

Cross-Probing: Interactive hierarchical cross-probing of LVS discrepancy is clearly displayed.

 

Expert Layout Editor

  • Seamlessly integrated with Gateway Schematic Editor for cross-probing and netlist-driven layout with parameterized cells (Pcells) using the LISA scripting language
  • Easy to use for all skill levels – online help for beginners, powerful scripting
    for experts
  • Customizable hotkeys, macros, and toolbars, in addition to direct technology file import from Virtuoso™ for GDS layer names, colors, and stipples
  • Guardian Physical Verification integrated DRC/LVS/LPE for interactive or batch operation
     
  • Real-time DRC rapidly validates layout “on the fly”
     
  • Supports Mentor and Cadence legacy DRC/LVS rule files with fast, automatic translation of Calibre™, Dracula™, and Diva™
  • Fast, intuitive LVS debugging with netlist cross-probing

 

Migration of Legacy Designs

  • Gateway Schematic Editor imports EDIF 2 0 0 designs and symbols
  • Expert Layout Editor reads Virtuoso™ tech files and reads/writes GDSII
  • Guardian DRC/LVS translates Calibre™ and Diva/Dracula runsets
  • SmartSpice reads HSPICE™ models, netlists, and commands

 

Integrated Design Flow

  • Circuit designers start with Gateway Schematic Editor to input or translate designs and drive SmartSpice for analysis, corners, and circuit optimization from its interactive window
  • After simulation and cross-probing, design is transferred to layout
  • Layout designers use the schematic-instantiated Parameterized Cells (Pcells) for DRC-correct layout and manual layout adjustments
  • Guardian physical verification provides interactive and batch DRC/LVS/LPE to close the design loop

 

Rev. 060313_16